• Journal of the Korean Institute of Navigation
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• v.14 no.4
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• pp.31-39
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• 1990

A systematic methodology for efficient implementation of processor arrays from regular iterative algorithms is proposed. One of the modern parallel processing array architectures is the Systolic arrays and we use it for processor arrays on this paper. On designing the systolic arrays, there are plenty of mapping functions which satisfy necessary conditions for its implementation to the time-space domain. In this paper, we sue a few conditions to reduce the total number of computable mapping functions efficiently. As a results of applying this methodology, efficient designs of systolic arrays could be done with considerable saving on design time and efforts.

• ETRI Journal
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• v.10 no.3
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• pp.125-140
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• 1988

Computational geometry has wide applications in pattern recognition, image processing, VLSI design, and computer graphics. Voronoi diagrams in computational geometry possess many important properites which are related to other geometric structures of a set of point. In this pater the design of systolic algorithms for the static and the dynamic Voronoi diagrams is considered. The major motivation for developing the systolic architecture is for VLSI implementation. A new systematic transform technique for designing systolic arrays, in particular, for the problem in computational geometry has been proposed. Following this procedure, a type T systolic array architecture and associated systolic algorithms have been designed for constructing Voronoi diagrams. The functions of the cells in the array are also specified. The resulting systolic array achieves the maximal throughput with O(n) computational complexity.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.10
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.26 no.3
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• pp.295-302
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• 1990

In this paper, a methodology for the automatic design of the optimal systolic arrays is proposed. Algorithm transformation is the main mathematical tool on which this methodology is based. Also, technique for partitioning algorithm into systolic arrays is presented. Algorithm partitioning is essential when the size of the computational problem is larger than the size of the array. This study results in (a) reduction of the design time of systolic arrays for given algorithms, (b) CRT display of the structures of systolic arrays, and (c) automatic designing of the optimal systolic array by the criteria such as the number of processing elements, bands, and communication paths. The procedure for these results was programmed using HP BASIC language on HP-9836 computer.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.11-20
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• 1994

We propose two architectures using two dimensional systolic arrays for the DCT/DST/DHT. One decomposes the N-point DCT/DST/DHT into even-and odd-numbered frequency samples, and then computes them independently at the same time. In addition, the proposed architecture can be used for the IDCT/IDST/IDHT. Anogher is the modified version for the DHT/IDHT. Two proposed architectures generate outputs sequentially using real multiplications and additions. As compared to the conventional methods the proposed systolic arrays exhibit many advantages in terms of simplicity of the processing element (PE), latency, and throughput. Teh simulation results using VHDL, international standard language for hardware description, show the effectiveness of the proposed architecture.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2222-2232
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• 1999

This paper proposed a Systolic Arrays architecture for computing edge detection on images. It is very difficult to be processed images to real time because of operations of local operators. Local operators for computing edge detection are to be used in many image processing tasks, involve replacing each pixel in an image with a value computed within a local neighborhood of that pixel. Computing such operators at the video rate requires a computing power which is not provided by conventional computer. Through computationally expensive, it is highly regular. Thus, this paper presents a systolic arrays for tasks such as edge detection and laplacian, which are defined in terms of local operators.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.41-48
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• 2020

In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim's systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1121-1124
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• 1987

Previous methods to map from a FORTRAN-like specification into a systolic array were difficult to find data dependencies because the specification was expressed and executed sequentially. Data-flow graph(DFG)s show data dependencies explicitly. In this paper we show a mapping tool from a DFG specification into a systolic array. We introduce the concept of a Systolic Pattern Stream(SPS) and use that concept to derive a systolic array.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.163-172
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• 1996

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.55-62
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• 1998

This Paper proposed a systolic Arrays architecture for computing Romberg's integration method. It consists of systolic arrays of two stage, one for integration by Trapezoidal rule and the other for integration by using Richardson's extrapolation. the proposed its architecture is very high speed and regular. This paper illustrates how " mathematical hardware " package, as well as software library routines, may be part of the mathematical problem solver's tool kit in the future.he future.