• Title/Summary/Keyword: system verification

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Customised feature set selection for automatic signature verification (서명자동검정을 위한 개인별 특징 세트 선택)

  • 배영래;조동욱;김지영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.7
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    • pp.1642-1653
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    • 1996
  • This paper covers feature extraction for automatic handwritten signature verification. Several major feature selection techniques are investigated from a practical perspective to realise an optimal signature verification system, and customised feature set selection based on set-on-set distance measurement is presented. The experimental results have proved the proposed methods to be efficient, offering considerably improved verification performance compared to conventional methods. Also, they dramatically reduce the processing complexity in the verification system.

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Simulation-based Design Verification for High-performance Computing System

  • Jeong Taikyeong T.
    • Journal of Korea Multimedia Society
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    • v.8 no.12
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    • pp.1605-1612
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    • 2005
  • This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

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A Study on the Virtual Reality Simulation Monitoring Verification System Available Wireless Communication Network (무선 통신망을 활용한 VR 시뮬레이션 관제상황 검증 시스템에 관한 연구)

  • Lee, Yang-Sun;Kang, Heau-Jo
    • Journal of Digital Contents Society
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    • v.7 no.3
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    • pp.193-197
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    • 2006
  • In this paper, We proposed monitoring verification system using virtual reality simulation technology in monitoring fields for peculiar environment. Also, we analyzed the proposed system about required technology issues and operation process. The proposed monitoring verification system available wireless communication network is expected that application is possible in medical treatment field or special dangerous article processing filed as well as monitoring verification of mobile electric railcar

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밀링가공의 절삭조건 검증시스템 개발

  • 김찬봉;양민양
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1993.10a
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    • pp.428-433
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    • 1993
  • In this paper, the fast algorithm to calculate cutting force of milling and its application to NC verification system have been studied. The fast force algorithm can calculate the maximum cutting force fastly during one revelotion of tool. The NC verification using the fast force algorithm can verify excessive cutting force which is the cause of deflection and breakage of tool, and can so adjust the feed rate as to manufacture with the maximum force criterion or maximum machining error criterion. So, the fast force algorithm has been added to the NC verification system, the NC verification system can verify the physical problems in NC code effectively.

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The Implementation of Hardware Verification System Using Fault Injection Method (결함 주입 방법을 이용한 하드웨어 검증시스템 구현)

  • Yoon, Kyung-Shub;Song, Myoung-Gyu;Lee, Jae-Heung
    • Journal of IKEEE
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    • v.15 no.4
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    • pp.267-273
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    • 2011
  • In hardware design, its stability and reliability are important, because a hardware error can cause serious damages or disaster. To improve stability and reliability, this paper presents the implementation of the hardware verification system using the fault injection method in PC environment. This paper presents a verification platform that can verify hardware system reliably and effectively, through a process to generate faults as well as insert input signals into the actual running system environment. The verification system is configured to connect a PC with a digital I/O card, and it can transmit or receive signals from the target system, as a verifier's intention. In addition, it can generate faults and inject them into the target system. And it can be monitored by displaying the received signals from the target system to the graphical wave signals. We can evaluate its reliability by analyzing the graphical wave signals. In this paper, the proposed verification system has been applied to the FPGA firmware of a nuclear power plant control system. As a result, we found its usefulness and reliability.

Web-based Draft Verification System for Injection Mold Design (사출금형설계를 위한 웹기반 구배 검증 시스템)

  • Yeon Kwang-Heum;Song In-Ho;Chung Sung-Chong
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.29 no.10 s.241
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    • pp.1353-1360
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    • 2005
  • Injection-molded products serve a wide range of applications in our modem lives and their significance is ever increasing. However, difficulty of communication among related companies under the present system results in increase of lead time and decrease of production efficiency. The objective of this paper is the development of a web-based draft verification system in mold design processes. Although several commercial CAD systems offer draft verification functions, those systems are very expensive and inadequate to perform collaborative works. For collaborative work under the distributed environment, the proposed system uses native file transforming of CAD data into optimal format by using the ACIS kernel and InterOp. Functions of draft verification modules are constructed over the ActiveX control using the visual C++ and OpenGL. Therefore, collaborators related to the development of a new product are able to verify the draft and undercut over the Internet without commercial CAD systems. The system helps to reduce production cost, errors and lead-time to the market. Performance of the system is confirmed through various case studies.

Practical Requirements and Verification Management for Requirements-based Development Process in Space Launch Vehicle Development Project (요구조건 기준의 개발 수행을 위한 우주발사체 개발사업의 실제적인 요구조건-검증 관리 체계)

  • Dong Hyun Cho;Jun Hyouk Jang;Il Sang Yoo
    • Journal of the Korean Society of Systems Engineering
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    • v.19 no.1
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    • pp.56-63
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    • 2023
  • For the success of system development, it is necessary to systematically manage the requirements that are the basis of system development and its verification results. In order to follow the principles of SE(Systems Engineering)-based V&V(Verification&Validation) process, requirements can be managed by securing the requirements and their establishments, design compliances, and verification compliances according to the system development lifecycle. Especially, in a large-complex system research and development project, such as a space launch vehicle development project, many participants establish, verify, and validate numerous requirements together during the project. Therefore, logical and systematic requirements management, including guarantee of data integrity, change history, and traceability, is very important for multiple participants to utilize numerous requirements together without errors. This paper introduces the practical requirements and verification management for the requirements-based development process in the space launch vehicle development project.

A Study on Applying a Consistent UML Model to Naval Combat System Software Using Model Verification System

  • Jung, Seung-Mo;Lee, Woo-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.27 no.5
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    • pp.109-116
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    • 2022
  • Recently, a model-based development method centered on highly readable and standardized UML (Unified Modeling Language) models has been applied to solve unclear communications in large-scale software development. However, it is difficult to apply consistent UML models depending on software developers' proficiency, understanding of models and modeling tools. In this paper, we propose a method for developing a Model Verification System to apply an consistent UML model to software development. Then, the developed Model Verification System is partially applied to the Naval Combat System Software development to prove its function. The Model Verification System provides automatic verification of models created by developers according to domain characteristics. If the Model Verification System proposed in this paper is used, It has the advantage of being able to apply the consistent UML model more easily to Naval Combat System Software Development.

Verification Test of Communication Protocol for Interface between EIS and LDTS (철도신호설비 상호간 정보전송을 위한 통신 프로토콜 검증시험)

  • 황종규;이재호;윤용기;신덕호
    • Journal of the Korean Society for Railway
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    • v.7 no.2
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    • pp.114-119
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    • 2004
  • According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

Noise Robust Speaker Verification Using Subband-Based Reliable Feature Selection (신뢰성 높은 서브밴드 특징벡터 선택을 이용한 잡음에 강인한 화자검증)

  • Kim, Sung-Tak;Ji, Mi-Kyong;Kim, Hoi-Rin
    • MALSORI
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    • no.63
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    • pp.125-137
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    • 2007
  • Recently, many techniques have been proposed to improve the noise robustness for speaker verification. In this paper, we consider the feature recombination technique in multi-band approach. In the conventional feature recombination for speaker verification, to compute the likelihoods of speaker models or universal background model, whole feature components are used. This computation method is not effective in a view point of multi-band approach. To deal with non-effectiveness of the conventional feature recombination technique, we introduce a subband likelihood computation, and propose a modified feature recombination using subband likelihoods. In decision step of speaker verification system in noise environments, a few very low likelihood scores of a speaker model or universal background model cause speaker verification system to make wrong decision. To overcome this problem, a reliable feature selection method is proposed. The low likelihood scores of unreliable feature are substituted by likelihood scores of the adaptive noise model. In here, this adaptive noise model is estimated by maximum a posteriori adaptation technique using noise features directly obtained from noisy test speech. The proposed method using subband-based reliable feature selection obtains better performance than conventional feature recombination system. The error reduction rate is more than 31 % compared with the feature recombination-based speaker verification system.

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