• Title/Summary/Keyword: synthesis algorithm

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FPGA Implementation of Riindael Algorithm according to the Three S-box Implementation Methods (Rijndael S-box의 세 가지 구현 방법에 따른 FPGA 설계)

  • 이윤경;박영수;전성익
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.281-284
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    • 2002
  • Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

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Optimum design of rotor supported on floating ring journal bearing by the enhanced artificial life optimization algorithm (인공생명 알고리듬을 이용한 프로팅 링 저널 베어링 지지 축계의 최적설계)

  • Song, Jin-Dea;Suk, Ho-Il;Yang, Bo-Suk
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11a
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    • pp.400.1-400
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    • 2002
  • This paper presents an optimum design of rotor-bearing system using a hybrid method to compute the solutions of optimization problem. The present hybrid algorithm, namely Enhanced Artificial Life Algorithm(EALA), is a synthesis of an artificial life algorithm(ALA) and the random tabu search(R-tabu) method. We applied EALA to the optimum design of rotor-shaft system supported by the floating ring journal bearings. (omitted)

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Computer-Aided Synthesis of Multiple-Output TANT Networks (컴퓨터에 의한 다출력 TANT 회로망의 구성)

  • 안광선;김항준
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.18 no.6
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    • pp.9-15
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    • 1981
  • A new algorithm is presented from minimiEing the gates cost and gate inputs cost for the multiple-output TANT networks. In this algorithm, multiple-output map is organized and multiple-output function is constructed by using combination of minterms in order of the number of head variables. Systematic combination is made by PSA algorithm, and so the total design procedure is simplified.

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USER BASED IMAGE SEGMENTATION FOR APPLICATION TO SATELLITE IMAGE

  • Im, Hyuk-Soon;Park, Sang-Sung;Shin, Young-Geun;Jang, Dong-Sik
    • Proceedings of the KSRS Conference
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    • 2008.10a
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    • pp.126-129
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    • 2008
  • In this paper, we proposed a method extracting an object from background of the satellite image. The image segmentation techniques have been widely studied for the technology to segment image and to synthesis segment object with other images. Proposed algorithm is to perform the edge detection of a selected object using genetic algorithm. We segment region of object based on detection edge using watershed algorithm. We separated background and object in indefinite region using gradual region merge from segment object. And, we make GUI for the application of the proposed algorithm to various tests. To demonstrate the effectiveness of the proposed method, several analysis on the satellite images are performed.

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A New Algorithm for An Efficient Implementation of the MDCT/IMDCT (MDCT/IMDCT의 효율적인 구현을 위한 새로운 알고리즘)

  • 조양기;이원표;인치호;김희석
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2471-2474
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    • 2003
  • The modified discrete cosine transform (MDCT) and its inverse transform (IMDCT) are employed in subband/transform coding schemes as the analysis/synthesis filter bank based on time domain aliasing cancellation (TDAC). And they are the most computational intensive operations in layer III of the MPEG audio coding standard. In this paper, we propose a new efficient algorithm for the MDCT/IMDCT computation. It is based on the MDCT/IMDCT computation algorithm using the discrete cosine transforms (DCTs), and it employs two discrete cosine transform of type II(DCT-II) to compute the MDCT/IMDCT. In addition to, it takes advantage of ability in calculating the MDCT/IMDCT computation, where the length of a data block is divisible by 4. The proposed algorithm in this paper requires less calculation complexity than the existing methods. Also, it can be implemented by the parallel structure,, and its structure is particularly suitable for VLSI realization.

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Algorithm for Concatenating Multiple Phonemic Units for Small Size Korean TTS Using RE-PSOLA Method

  • Bak, Il-Suh;Jo, Cheol-Woo
    • Speech Sciences
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    • v.10 no.1
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    • pp.85-94
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    • 2003
  • In this paper an algorithm to reduce the size of Text-to-Speech database is proposed. The algorithm is based on the characteristics of Korean phonemic units. From the initial database, a reduced phoneme unit set is induced by articulatory similarity of concatenating phonemes. Speech data is read by one female announcer for 1000 phonetically balanced sentences. All the recorded speech is then segmented by phoneticians. Total size of the original speech data is about 640 MB including laryngograph signal. To synthesize wave, RE-PSOLA (Residual-Excited Pitch Synchronous Overlap and Add Method) was used. The voice quality of synthesized speech was compared with original speech in terms of spectrographic informations and objective tests. The quality of the synthesized speech is not much degraded when the size of synthesis DB was reduced from 320 MB to 82 MB.

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Design of an Area-efficient DCME Algorithm for High-speed Reed-Solomon Decoder (고속 Reed-Solomon 복호기를 위한 면적 효율적인 DCME 알고리즘 설계)

  • Kang, Sung Jin
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.4
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    • pp.7-13
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    • 2014
  • In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

Concept Optimization for Mechanical Product Using Genetic Algorithm

  • Huang Hong Zhong;Bo Rui Feng;Fan Xiang Feng
    • Journal of Mechanical Science and Technology
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    • v.19 no.5
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    • pp.1072-1079
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    • 2005
  • Conceptual design is the first step in the overall process of product design. Its intrinsic uncertainty, imprecision, and lack of information lead to the fact that current conceptual design activities in engineering have not been computerized and very few CAD systems are available to support conceptual design. In most of the current intelligent design systems, approach of principle synthesis, such as morphology matrix, bond graphic, or design catalogues, is usually adopted to deal with the concept generation, in which optional concepts are generally combined and enumerated through function analysis. However, as a large number of concepts are generated, it is difficult to evaluate and optimize these design candidates using regular algorithm. It is necessary to develop a new approach or a tool to solve the concept generation. Generally speaking, concept generation is a problem of concept synthesis. In substance, this process of developing design candidate is a combinatorial optimization process, viz., the process of concept generation can be regarded as a solution for a state-place composed of multi-concepts. In this paper, genetic algorithm is utilized as a feasible tool to solve the problem of combinatorial optimization in concept generation, in which the encoding method of morphology matrix based on function analysis is applied, and a sequence of optimal concepts are generated through the search and iterative process which is controlled by genetic operators, including selection, crossover, mutation, and reproduction in GA. Several crucial problems on GA are discussed in this paper, such as the calculation of fitness value and the criteria for heredity termination, which have a heavy effect on selection of better concepts. The feasibility and intellectualization of the proposed approach are demonstrated with an engineering case. In this work concept generation is implemented using GA, which can facilitate not only generating several better concepts, but also selecting the best concept. Thus optimal concepts can be conveniently developed and design efficiency can be greatly improved.

Smart grid and nuclear power plant security by integrating cryptographic hardware chip

  • Kumar, Niraj;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • v.53 no.10
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    • pp.3327-3334
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    • 2021
  • Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

On a Pitch Alteration Method using Scaling the Harmonics Compensated with the Phase for Speech Synthesis (위상 보상된 고조파 스케일링에 의한 음성합성용 피치변경법)

  • Bae, Myung-Jin
    • The Journal of the Acoustical Society of Korea
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    • v.13 no.6
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    • pp.91-97
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    • 1994
  • In speech processing, the waveform codings are concerned with simply preserving the waveform of signal through a redundancy reduction process. In the case of speech synthesis, the waveform codings with high quality are mainly used to the synthesis by analysis. Because the parameters of this coding are not classified as both excitation and vocal tract, it is difficult to apply the waveform coding to the synthesis by rule. Thus, in order to apply the waveform coding to synthesis by rule, it is necessary to alter the pitches. In this paper, we proposed a new pitch alteration method that can change the pitch period in waveform coding by dividing the speech signals into the vocal tract and excitation parameters. This method is a time-frequency domain method preserving the phase component of the waveform in time domain and the magnitude component in frequency domain. Thus, it is possible that the waveform coding is carried out the synthesis by rule in speech processing. In case of using the algorithm, we can obtain spectrum distortion with $2.94\%$. That is, the spectrum distortion is decreased more $5.06\%$ than that of the pitch alteration method in time domain.

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