• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.07a
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• pp.593-595
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• 2020

본 논문에서는 5G NR 시스템을 위한 동기 신호를 이용한 cell ID 검출 방법에 대한 성능을 비교하였다. 5G NR(fifth-generation new radio) 시스템의 송신기는 SS/PBCH (synchronization signal/physical broadcast channel) 블록을 송신하며, 수신기는 수신된 SS/PBCH 블록을 이용하여 주파수 및 타이밍 오프셋 (frequency and timing offset)을 추정 할 수 있으며, cell ID (cell identity)는 PSS (primary synchronization signal)와 SSS (secondary synchronization signal)를 통해 검출할 수 있다. 본 논문에서는 cell ID 를 검출할 수 있는 방법으로서 2-stage 디코딩 방법과 결합 최대우도 결정 규칙 (joint maximum-likelihood decision rule: joint ML) 디코딩 방법을 사용하였다. Joint ML 디코딩 방법은 2-stage 디코딩 방법에 비해 더 좋은 검출 성능을 보이지만, 복잡도 측면에서는 2-stage 디코딩 방법이 joint ML 디코딩 방법에 비해 더 낮은 복잡도를 갖는 것을 확인하였다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.4
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• pp.51-57
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• 2013

Research on calibration of array antenna has become a hot spot in the area of signal processing and it is necessary to obtain the phase mismatch of each antenna channel. This paper presents a new calibration method for an array antenna system. In order to calibrate the phase mismatch of each antenna channel, we used primary synchronization signal (PSS) which exists in LTE downlink frame. Primary synchronization signal (PSS) is based on a Zadoff-Chu sequence which has a good correlation characteristic. By using correlation calculation, we can extract primary synchronization signal (PSS). After extracting primary synchronization signal (PSS), we use it to calibrate and reduce the phase errors of each antenna channel. In order to verify the new array antenna calibration algorithm which is proposed in this paper, we have simulated the proposed algorithm by using MATLAB. The array antenna system consists of two antenna elements. The phase mismatch of first antenna and second antenna is calculated accurately by proposed algorithm in the experiment test. Theory analysis and MATLAB simulation results are shown to verify the calibration algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1405-1408
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• 2008

Synchronization signal circuit system for low cross-talk stereoscopic display. We proposed the employment of the scanning beams of any adjacent scanning regions gradually scan from upper to down direction of the LED backlight panel.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4871-4877
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• 2015

This article presents a circuit and a system for IEEE 1588 based clock synchronization to generate a very accurate frequency signal required in femtocell devices. A prototype board and the experimental environment to verify the functions and to evaluate the performance are explained to verify the feasibility of the proposed synchronization system. To make low-cost femtocells without constraints on the place of installation, it is very important to study on the practical implementation of synchronization system based on IEEE 1588. The experimental result shows that the synchronization errors between -16 ns and 9 ns are guaranteed over the network of femtocell devices with the proposed synchronization circuits, thus the synchronization criteria of the 3GPP HNB are met.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.575-578
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• 2003

In this paper, we introduce a hyper-chaos secure communication method using Hyper-chaos consist of State-Controlled Cellular Neural Network (SC-CNN). A hyper-chaos circuit is created by applying identical n-double scroll with weak coupled method to each cell. Hyper-chaos synchronization was achieved using embedding synchronization between the transmitter and receiver about in SC CNN. And then, we accomplish secure communication by synthesizing the desired information with a hyper-chaos circuit by embedding the information signal to the only one state variable instead of all state variables in the driven-synchronization method. After transmitting the synthesized signal to the identical channel, we confirm secure communication by separating the information signal and the hyper-chaos signal in the receiver.

• ETRI Journal
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• v.34 no.1
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• pp.122-125
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• 2012

A video signal through a high-density optical link has been demonstrated to show the reliability of optical link for high-data-rate transmission. To reduce optical point-to-point links, an electrical link has been utilized for control and clock signaling. The latency and flicker with background noise occurred during the transferring of data across the optical link due to electrical-to-optical with optical-to-electrical conversions. The proposed synchronization technology combined with a flicker and denoising algorithm has given good results and can be applied in high-definition serial data interface (HD-SDI), ultra-HD-SDI, and HD multimedia interface transmission system applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.5
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• pp.980-987
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• 2009

A timing synchronization method is presented for IEEE 802.11a wireless OFDM system. First the signal detection is achieved by measuring the moving energy of the received OFDM signal in two consecutive windows. By measuring the correlation between the short training signal and received envelope signal, fine OFDM symbol synchronization can be acquired. The variance and average value of the correlation value is acquired. And the theoretical values are compared with computer simulation results.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.476-484
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• 2018

The high capacity audio watermarking algorithms are facing a main challenge in satisfying the robustness against attacks especially on de-synchronization attacks. In this paper, a robust and a high capacity algorithm is proposed using segment selection, Stationary Wavelet Transform (SWT) and the Quantization Index Modulation (QIM) techniques along with new synchronization mechanism. The proposed algorithm provides enhanced trade-off between robustness, imperceptibility, and capacity. The achieved watermarking improves the reliability of the available watermarking methods and shows high robustness towards signal processing (manipulating) attacks especially the de-synchronization attacks such as cropping, jittering, and zero inserting attacks. For imperceptibility evaluation, high signal to noise ratio values of above 22 dB has been achieved. Also subjective test with volunteer listeners shows that the proposed method has high imperceptibility with Subjective Difference Grade (SDG) of 4.76. Meanwhile, high rational capacity up to 176.4 bps is also achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.