• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.197-200
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• 1998

Three switched-capacitor(SC) networks are presented including series-parallel capacitor set, reversed-switched-capacitor network and push-pull switched-capacitor network, the performances of which are discussed. Combining the SC networks with traditional DC-DC converters, we form several new topologies. Experiment and analyzed results show that the behavior of a DC-DC converter with large voltage ratio can be improved. A wider voltage conversion range is also obtained.

• 정보처리학회논문지C
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• 제11C권1호
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• pp.99-108
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• 2004

본 논문에서는 공장자동화를 위한 제어네트워크로서의 스위칭 이더넷 네트워크의 성능을 분석한다. 스위칭 이더넷은 네트워크상에서의 충돌을 없앰으로써 실시간 데이터의 전송을 가능하게 하여 준다. 공장자동화 제어네트워크는 일반 컴퓨터 네트워크와는 달리 전송되는 데이터의 양은 적은 반면 실시간 전송을 요한다. 본 논문에서는 이더넷 스위치를 이용한 선형 및 트리 토폴로지의 네트워크에서 제어시스템이 요구하는 전송지연시간 요구를 만족하는지에 대해 분석한다.

• 한국컴퓨터정보학회논문지
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• 제1권1호
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• pp.25-36
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• 1996

본 논문은 격자 구조 회선 교환 망에서 발생할 수 있는 호 차단 확률 및 failure model을 설정하여 신뢰도를 분석하였다 특히 failure model에서는 link failure 모델을 고려하였다. 대상 모델은.flooding search routing 방식을 사용하여 패킷을 통화 대상자 노드에 전송하였다. 이때. 각 링크failure는 독립적이라고 가정하였다. 이와 같은 failure모델의 성능을 평가하기 위한 방법으로서 joint probability를 이용하여 소규모 격자 구조 회선 교환망의 신뢰도를 분석해 보았으며. 이를 시뮬레이션 한 값과 비교해 보았다 또한. 통신망에서 주요한 성능 지표중 하나8! 호 차단 확률을 구하여 회선망의 신뢰도를 평가하였다.

• 전자공학회논문지B
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• 제31B권5호
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• pp.123-133
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• 1994

This paper presents an output arbitrator for input buffering ATM (Asynchronous Transfer Mode) switches using neural networks. To avoid blocking in ATM switches with blocking characteristics, it is required to buffer ATM cells in input buffer and to schedule them. The N$\times$N request matrix is divided into N/16 submatrices in order to get rid of internal blocking systematically in scheduling phase. The submatrices are grouped into N/4 groups, and the cells in each group are switched alternatively. As the window size of input buffer is increases, the number of input cells switched in a time slot approaches to N. The selection of nonblocking cells to be switched is done by neural network modules. N/4 neural network modules are operated simultaneously. Fast selection can be achieved by massive parallelism of neural networks. The neural networks have 4N neurons and 14N connection. The proposed method is implemented in C language, and the simulation result confirms the feasibility of this method.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2009년도 정보통신설비 학술대회
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• pp.91-96
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• 2009

In Public Switched Telephone Networks(PSTN) number portability is implemented by utilizing Intelligent Network(IN) functions for number mapping. And voice over IP(VoIP) and IP Multimedia Subsystem(IMS) networks can deploy number portability by using E.164 Number Mapping(ENUM). This paper discuss the possibility of using E.164 Number Mapping(ENUM) for number portability in voice over IP/IP Multimedia Subsystem and Public Switched Telephone Networks, eliminating the need for Number Portability Database(NPDB) for number portability routing data in Public Switched Telephone Networks.

• 전자공학회논문지A
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• 제32A권8호
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• pp.1-10
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• 1995

We have analyzed the reliability of failure models in circuit-switched networks. These models are grid topology circuit-switched networks, and each node transmits a packet to a destination node using a Flooding routing method. We have assumed that the failure of each link and node is independent. We have considered two method to analyze reliability in these models : The Karnaugh Map method and joint probability method. In this two method, we have analyzed the reliability in a small grid topology circuit switched network by a joint probability method, and comared analytic results with simulated ones. For a large grid enormous. So, we have evaluated the reliability of the network by computer simulation techniques. As results, we have found that the analytic results are very close to simulated ones in a small grid topology circuit switched network. And, we have found that network reliability decreases exponentially, according to increment of link or node failure, and network reliability is almost linearly decreased according to increment of the number of links, by which call has passed. Finally, we have found an interesting result that nodes in a center of the network are superior to the other nodes from the reliability point of view.

• 전자공학회논문지A
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• 제31A권12호
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• pp.1-8
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• 1994

In this paper, we hve compare the performance of DAR(Dynamic Adaptive Routing) with that of FSR(Flooding Search Routing) to select an adequate routing protocol in circuit-switched networs. As a performance factor, we have considered call setup time, which is the key factor of performance evaluation in circuit switched networks. We have evaluated the performance of two methods in grid topology circuit-switched networks using a commn channel signaling scheme, as application examples. As results, FSR method shows better performance than DAR method under light traffic load, when the number of links by which call has passed increases, but DAR method represents better performance than FSR method under heavy traffic load or large networks because of redundant packets.

• 제어로봇시스템학회논문지
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• 제6권8호
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• pp.666-671
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• 2000

With the current advances in optical WDM (Wavelength Division Multiplexing) networking technologies and the increasing demand for network bandwidth the Next Generation Internet is expected to be a network that runs IP(Internet Protocol) directly over WDM-based optical networks. The network control architecture for the IP over WDM networks is different from that of traditional Internet since the underlying WDM devices have more constraints than electronic IP routers such as the lack of optical buffers and wavelength continuity property etc. In this paper we introduce several architectural models for implementing IP over WDM networks and propose an integrated network control framework for the IP over WDM networks. This framework leverages the traffic engineering control architecture for the MPLS (Multi-Protocol Label Switching) networks and is mainly developed for the IP over packet-switched WDM networks. We also report several preliminary simulation results of contention resolution schemes in the packet-switched WDM networks.

• ETRI Journal
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• 제31권2호
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• 안보군사학연구
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• 통권1호
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• pp.345-360
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• 2003

To build an information oriented armed forces, the Korean military telecommunication networks adopt TCP/IP standard communication infrastructures based on ATM packet switched networks. Utilizing this network infrastructure, the Korean armed forces also applies to the areas of battleship management for efficient operation command controls and resource management for efficient resource allocations. In this military communication networks, it is essential to determine the least cost network topology under equal performance and reliability constraints. Basically, this type of communication network design problem is known in the literature as an NP Hard problem. As the number of network node increases, it is very hard to obtain an optimal solution in polynomial time. Therefore, it is reasonable to use a heuristic algorithm which provides a good solution with minimal computational efforts. In this study, we developed a simulated annealing based heuristic algorithm which can be utilized for the design of military communication networks. The developed algorithm provides a good packet switched network topology which satisfies a given set of performance and reliability constraints with reasonable computation times.