• Journal of Power Electronics
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• v.5 no.1
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• pp.67-75
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• 2005

A high efficiency ZVS PWM asymmetrical half bridge converter for a plasma display panel (PDP) sustaining power modules is proposed in this paper. To achieve the ZVS of power switches for the wide load range, a small additional inductor L/sub 1kg/, which also acts as an output filter inductor, is serially inserted into the transformer's primary side. At that point, to solve the problem of ringing in the secondary rectifier caused by L/sub 1kg/, the proposed circuit employs a structure without the output filter inductor, which helps the voltages across rectifier diodes to be clamped at the output voltage. Therefore, no dissipative RC (resistor capacitor) snubber for rectifier diodes is needed and a high efficiency as well as low noise output voltage can be realized. In addition, since it has no large output inductor filter, the asymmetrical half bridge converter features a simpler structure, lower cost, less mass, and lighter weight. In addition, since all energy stored in L/sub 1kg/ is transferred to the output side, the circulating energy problem can be effectively solved. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385Vdc/170Vdc prototype are presented.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.349-352
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• 2003

A personal low-frequency stimulator is a portable device to relax muscle pains of a person. The stimulator generates combined low-frequency pulses to be applied to pads attached to painful muscles. This paper reports a development of such device with its characteristic analyses. The major components of our stimulator are MCU, high-voltage generating circuit part, high-voltage switching circuit part, input switch part and display unit. High-voltage generating circuit is designed by using a boost converter circuit and allows user control of the output voltage. High-voltage switching circuit, controlled by MCU, generates output voltage to be applied to pads. Input switch part is composed of power supply, intensity selection, mode selection and memory. Display unit adopts a text LCD module to display modes, Intensity, output frequency and user set-up time. Our designed safety circuit, to protect human body from possible electric shock, slowly increases the output voltage to the selected output intensity. It continuously checks the output pulse shape and disable the output when dangerous pulses are detected. This paper also shows some experimental results.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.387-392
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• 1990

In this papers, SPICE which is widely used in analysis of general circuit and simulation in electric and electrical field is applied to DC-DC converter. Be selected Forward which is widely used as SMPS(Switched Mode Power Supply) amang DC-DC converter, and showed the aveformer, we know that the converter is operated in normal. Including the control circuit in converter, by controlling the duty ratio of switch, we know that the output voltages is staple from the transient state of convwrter. Also, comparing SPICE simulation with experiment, the validity of simulate is showed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.411-420
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• 1991

In this paper, SPICE program which is widely used in analysis of general circuit on electronic and electrical field has been applied to DC-DC converter. We have selected Forward type which is widely used us SMPS(Switched Mode Power Supply) of various electronic equipments, and have confirmed the waveforms of circuit operation, transfer of energy and resetting in transformer. And the procedure which the output voltage of converter, including the control circuit, has been stabilized from the transient state to the steady state by controlling the duty ratio of switch is presented. We have compared SPICE simulation with experiment and have verified the validity of SPICE simulation.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.97-105
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• 2020

Recently, as the data speed and operating frequencies of Ethernet keeps increasing, electro magnetic interference (EMI) also becomes increasing. The generation of such EMI will cause malfunction of near electronic devices. In this study, EMI filters were applied to reduce the EMI generated by DC-DC SMPS (switching mode power supply), which is the main cause of EMI generation of Ethernet switch. As the EMI filter, MLCCs with excellent withstanding voltage characteristics were used, which had advantages in miniaturization and mass production. Two types of EMI MLCC filters were used, which are X-capacitor and X, Y-capacitor. X-capacitor was composed of 2 MLCCs with 10 nF and 100 nF capacity and 1 Mylar capacitor. Y-capacitor was consisted of 6 MLCCs with a capacity of 27 nF. When only X-capacitor was applied as EMI filter, the conductive EMI field strength exceeded the allowable limit in frequency range of 150 kHz ~ 30 MHz. The radiative EMI also showed high EMI strength and very small allowable margin at the specific frequencies. When the X and Y-capacitors were applied, the conductive EMI was greatly reduced, and the radiation EMI was also found to have sufficient margin. In addition, X, Y-capacitors showed very high insulation resistance and withstanding resistance performances. In conclusion, EMI X, Y-capacitors using MLCCs reduced the EMI noise effectively and showed excellent electrical reliability.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

• Proceedings of the KIEE Conference
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• 2004.04a
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• pp.133-135
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• 2004

As a result of the recent advances in magnetic materials, the Magnetic Amplifier(Magamp) technique is one of the reliable and cost-effective postregulation method for multiple-output power supply. This is true for high-current postregulated output since at highter output current the efficiency of linear postregulation is unacceptably low, while the complexity of more efficient switch mode postregulator is associated with a significant cost. Magamp have some advantages of higher power density, simple control circuit, good regulation, high frequency and high performance. In this paper, Operation principle of proposed approach and a performance of magamp control circuit with TL431 is described. The comparative analysis of magamp circuit and buck regulator circuit with 20W load condition is conducted. Experimental verifications on multi-output flyback converter are conducted. Simulations and experimental results show that the proposed approach is efficiency and voltage regulation of the auxiliary output is excellent.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.