• 제목/요약/키워드: switch mode power supply

검색결과 86건 처리시간 0.026초

A High Efficiency ZVS PWM Asymmetrical Half Bridge Converter for Plasma Display Panel Sustaining Power Modules

  • Han Sang-Kyoo;Moon Gun-Woo;Youn Myung-Joong
    • Journal of Power Electronics
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    • 제5권1호
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    • pp.67-75
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    • 2005
  • A high efficiency ZVS PWM asymmetrical half bridge converter for a plasma display panel (PDP) sustaining power modules is proposed in this paper. To achieve the ZVS of power switches for the wide load range, a small additional inductor L/sub 1kg/, which also acts as an output filter inductor, is serially inserted into the transformer's primary side. At that point, to solve the problem of ringing in the secondary rectifier caused by L/sub 1kg/, the proposed circuit employs a structure without the output filter inductor, which helps the voltages across rectifier diodes to be clamped at the output voltage. Therefore, no dissipative RC (resistor capacitor) snubber for rectifier diodes is needed and a high efficiency as well as low noise output voltage can be realized. In addition, since it has no large output inductor filter, the asymmetrical half bridge converter features a simpler structure, lower cost, less mass, and lighter weight. In addition, since all energy stored in L/sub 1kg/ is transferred to the output side, the circulating energy problem can be effectively solved. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385Vdc/170Vdc prototype are presented.

개인용 저주파 자극기의 특성분석 및 Prototype개발 (A Prototype Development of Personal Low-frequency Stimulator with Characteristic Analysis)

  • 이기송;이동하;유재택
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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    • pp.349-352
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    • 2003
  • A personal low-frequency stimulator is a portable device to relax muscle pains of a person. The stimulator generates combined low-frequency pulses to be applied to pads attached to painful muscles. This paper reports a development of such device with its characteristic analyses. The major components of our stimulator are MCU, high-voltage generating circuit part, high-voltage switching circuit part, input switch part and display unit. High-voltage generating circuit is designed by using a boost converter circuit and allows user control of the output voltage. High-voltage switching circuit, controlled by MCU, generates output voltage to be applied to pads. Input switch part is composed of power supply, intensity selection, mode selection and memory. Display unit adopts a text LCD module to display modes, Intensity, output frequency and user set-up time. Our designed safety circuit, to protect human body from possible electric shock, slowly increases the output voltage to the selected output intensity. It continuously checks the output pulse shape and disable the output when dangerous pulses are detected. This paper also shows some experimental results.

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SPICE 를 이용한 Forward DC-DC 콘버어터 해석 (An analysis of Forward DC-DC Converter using SPICE program)

  • 김희준;이영선
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1990년도 하계학술대회 논문집
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    • pp.387-392
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    • 1990
  • In this papers, SPICE which is widely used in analysis of general circuit and simulation in electric and electrical field is applied to DC-DC converter. Be selected Forward which is widely used as SMPS(Switched Mode Power Supply) amang DC-DC converter, and showed the aveformer, we know that the converter is operated in normal. Including the control circuit in converter, by controlling the duty ratio of switch, we know that the output voltages is staple from the transient state of convwrter. Also, comparing SPICE simulation with experiment, the validity of simulate is showed.

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SPICE를 이용한 Forward DC-DC 콘버어터 해석 (An Analysis of Forward DC-DC Converter Using SPICE Program)

  • 김희준;안태영;이영선
    • 전자공학회논문지B
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    • 제28B권5호
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    • pp.411-420
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    • 1991
  • In this paper, SPICE program which is widely used in analysis of general circuit on electronic and electrical field has been applied to DC-DC converter. We have selected Forward type which is widely used us SMPS(Switched Mode Power Supply) of various electronic equipments, and have confirmed the waveforms of circuit operation, transfer of energy and resetting in transformer. And the procedure which the output voltage of converter, including the control circuit, has been stabilized from the transient state to the steady state by controlling the duty ratio of switch is presented. We have compared SPICE simulation with experiment and have verified the validity of SPICE simulation.

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A 900 MHz Zero-IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

  • Kim, Changwan;Lee, Seungsik;Choi, Sangsung
    • ETRI Journal
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    • 제36권3호
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    • pp.352-360
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    • 2014
  • This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

SMPS용 전력소자가 내장된 PWM IC 설계에 관한 연구 (The Study on the design of PWM IC with Power Device for SMPS application)

  • 임동주;구용서
    • 전기전자학회논문지
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    • 제8권1호
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    • pp.152-159
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    • 2004
  • 본 연구에서는 Bi-DMOS 기술을 이용하여 SMPS용 고내압 스윗칭 전력소자 내장형 one-chip PWM IC를 설계하였다. 기준전압회로는 다양한 온도와 공급전압의 변화에도 일정한 전압(5V)을 발생시킬 수 있도록 설계하였고, 오차 증폭기의 경우, 높은 dc gain$({\simeq}65.7db)$, unity frequency$({\simeq}189Khz)$, 적절한 $PM({\simeq}76)$를 가지면서 높은 입력저항을 갖도록 설계하였다. 비교기는 2단 구성으로 설계를 하였고, 삼각파 발생회로 경우, 외부 저항과 캐패시터를 이용해서 발진 주파수(20K), output swing 폭(3.5V)을 갖는 삼각파를 발생시켰다. 스윗칭 파워소자는 SOI 기판을 사용하고, 확장 드레인 영역의 길이와 도핑 농도를 적절히 조정, 350V급 내압을 갖는 n-LDMOSFET을 설계 하였다. 최종적으로, layout은 각 소자에 대한 디자인 룰(2um 설계 룰)을 설정하였고, Bi-DMOS 공정 기술을 바탕으로 PWM IC 회로와 n-LDMOSFET one-chip IC를 설계하였다.

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MLCC를 이용한 SMPS의 EMI 저감 설계 (Design of EMI Reduction of SMPS Using MLCC Filters)

  • 최병인;좌성훈
    • 마이크로전자및패키징학회지
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    • 제27권4호
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    • pp.97-105
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    • 2020
  • 최근 초고속 이더넷(ethernet)의 데이터 및 동작주파수 속도가 증가하고 있으며, 이에 따라 EMI(electromagnetic interference)가 증가하고 있다. 이러한 EMI의 발생은 주변 전자기기들에 영향을 미쳐 오동작 원인이 될 가능성이 높다. 본 연구에서는 고속 이더넷 스위치 EMI 발생의 주요 원인인 DC-DC SMPS (switching mode power supply)에서 발생하는 EMI 저감을 위해 EMI 필터를 적용하였다. EMI 필터소자는 소형화, 양산화에 장점을 가지며, 내전압(dielectric voltage) 특성이 우수한 MLCC (multi-layer ceramic capacitor)를 사용하였다. MLCC 필터는 X-커패시터 및 X, Y-커패시터로 구성되어 있다. X-커패시터는 10 nF 및 100 nF 용량의 2개의 MLCC와 1개의 마일러 콘덴서(mylar capacitor)로 구성하였다. Y-커패시터는 용량 27 nF의 6개의 MLCC를 사용하여 구성하였다. X-커패시터만을 EMI 필터로 적용한 경우, 전도성(conductive) EMI는 150 kHz ~ 30 MHz의 주파수 대역에서 EMI 전계강도가 허용 한계치를 초과함을 알 수 있었다. 또한 방사성(radiative) EMI도 특정 주파수에서 EMI 전계 강도가 높고, 허용 마진폭도 매우 적음을 알 수 있었다. 반면 X, Y-커패시터를 적용하였을 경우, 전 주파수 대역에서 전도성 EMI가 크게 감소하였으며, 방사선 EMI도 충분한 마진이 확보됨을 알 수 있었다. 또한 X, Y-커패시터의 전기적인 신뢰성을 평가하기 위하여 절연 저항(insulation resistance) 및 내전압 성능을 측정하였으며, 절연 저항 및 내저항 성능이 모두 전기적 신뢰성 기준을 만족함을 알 수 있었다. 결론적으로 MLCC 필터를 X, Y-커패시터로 사용하여 전도성 및 방사성 EMI 노이즈가 효과적으로 감소되었고, 우수한 전기적인 신뢰성도 확보됨을 알 수 있었다.

Voltage Scaling 기반의 저전력 전류메모리 회로 설계 (Design of Low Power Current Memory Circuit based on Voltage Scaling)

  • 여성대;김종운;조태일;조승일;김성권
    • 한국전자통신학회논문지
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    • 제11권2호
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    • pp.159-164
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    • 2016
  • 무선통신시스템은 한정된 에너지를 갖는 배터리를 사용하기 때문에 저전력 회로로 구현되어야 하며, 이를 위하여 주파수와 상관없이 일정한 전력을 나타내는 전류모드 회로가 연구되어왔다. 본 논문에서는 초저전력 동작이 가능하도록 Dynamic Voltage Scaling 전원을 유도하며, 전류모드 신호처리 중 메모리 동작에서 저장된 에너지가 누설되는 Clock-Feedthrough 문제를 최소화하는 전류메모리 회로를 제안한다. $0.35{\mu}m$ 공정의 BSIM3 모델로 Near-threshold 영역의 전원 전압을 사용한 시뮬레이션을 진행한 결과, 1MHz의 스위칭 동작에서 $2{\mu}m$의 메모리 MOS Width, $0.3{\mu}m$의 스위치 MOS Width, $13{\mu}m$의 Dummy MOS Width로 설계할 때, Clock-Feedthrough의 영향을 최소화시킬 수 있었으며 1.2V의 Near-threshold 전원전압에서 소비전력은 $3.7{\mu}W$가 계산되었다.

다출력 전원회로의 안정화를 위한 자기증폭기의 특성해석 (Analysis on the Characteristics of Magnetic Amplifier for Multi-output Postregulation)

  • 김철진;이관용;홍대식;김영태;백수현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.133-135
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    • 2004
  • As a result of the recent advances in magnetic materials, the Magnetic Amplifier(Magamp) technique is one of the reliable and cost-effective postregulation method for multiple-output power supply. This is true for high-current postregulated output since at highter output current the efficiency of linear postregulation is unacceptably low, while the complexity of more efficient switch mode postregulator is associated with a significant cost. Magamp have some advantages of higher power density, simple control circuit, good regulation, high frequency and high performance. In this paper, Operation principle of proposed approach and a performance of magamp control circuit with TL431 is described. The comparative analysis of magamp circuit and buck regulator circuit with 20W load condition is conducted. Experimental verifications on multi-output flyback converter are conducted. Simulations and experimental results show that the proposed approach is efficiency and voltage regulation of the auxiliary output is excellent.

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A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

  • Abbasizadeh, Hamed;Lee, Dong-Soo;Yoo, Sang-Sun;Kim, Joon-Tae;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권6호
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    • pp.760-770
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    • 2016
  • A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.