• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.937-939
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• 2009

In this paper, we report electrical properties of OTFTs made by ink-jet printing with polyvinylphenol (PVP) for bank layer and bis(triisopropylsilylenthynyl) pentacene (TIPS-pentacene) for semiconductor. We could achieve better crystallization and surface uniformity of TIPS pentacene by employing PVP bank layer. The OTFT with PVP bank layer exhibited an field-effect mobility of 0.18 $cm^2$/Vs, current on/off ratio of $2.09{\times}10^5$, and subthreshold slope of 0.42 V/decane.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.318-321
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• 2009

We have studied transparent top gate Al-Zn-Sn-O (AZTO) TFTs with an $Al_2O_3$ protective layer (PL) on an active layer. We also fabricated a transparent 2.5 inch QCIF+AMOLED display panel using the AZTO TFT back-plane. The AZTO active layers were deposited by RF magnetron sputtering at room temperature and the PL was deposited by ALD with two different processes. The mobility and subthreshold slope were superior in the cases of the vacuum annealing and the oxygen plasma PL compared to the $O_2$ annealing and the water vapor PL, however, the bias stability was excellent for the TFTs of the $O_2$ annealing and the water vapor PL.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.896-898
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• 2009

The printed electrodes of organic thin-film transistors (OTFTs) were fabricated by screen printing using nanoparticle silver pastes. The screen printed OTFT corresponds to channel lengths between 7.6 to 82.6 ${\mu}m$ (designed L=10 to 80 ${\mu}m$) on the $150{\times}150mm^2$ paper. The channel length deviations for 40 to 80 ${\mu}m$ patterns were less than 5 %. However, the channel lengths for 10 to 30 ${\mu}m$ patterns were increased by 20 %. The screen printed bis(triisopropyl-silylethynyl) pentacene (TIPS-pentacene) OTFTs obtained had a field-effect mobility as large as 0.08 (${\pm}0.02$) $cm^2$/Vs, an on/off current ratio of $10^5$ and a subthreshold slope of 1.95 V/decade.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1002-1004
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• 2009

Solution-processed indium-gallium-zinc-oxide thin-film transistors were fabricated by sol-gel method. By a combinatorial study of InGaZnO multi-component system, optimum molar ratio of In, Ga, and Zn has been selected. By adjusting the In:Ga:Zn molar ratio, TFTs with field-effect mobility of 0.5 ~ 1.5 $cm^2$/V-s, threshold voltage of -5 ~ 5 V, and subthreshold slope of 1.5 ~ 2.5 V/decade were achieved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• ETRI Journal
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• v.11 no.2
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• pp.109-119
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• 1989

Based on the 2-dimensional charge-control simulation[4], a purely analytical model for MODFET's is proposed. In this model, proper treatment of the diffusion effect in the 2-DEG transport due to the gradual channel opening along the 2-DEG channel was made to explain the enhanced mobility and increased thershold voltage. The channel thickness and gate capacitance are experssed as functions of gate vlotage including subthreshold characteristics of the MODFET's analytically. By introducing the finite channel opening and an effective channel-length modulation, the slope of the saturation region of the I-V curves was modeled. The smooth transition of the I-V curves from linear-to-saturation region of the I-V curves was possible using the continuous Troffimenkoff-type of field-dependent mobility. Furthermore, a correction factor f was introduced to account for the finite transtition section forming between the GCA and the saturated section. This factor removes the large discrepanicies in the saturation region fo the I-V curves presicted by existing 1-dimensional models. The fitting parameters chosen in our model were found to be predictable and vary over relatively small range of values.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.512-518
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• 2006

In this paper, we investigated the deposition of pentacene thin film on a large area substrate by Organic Vapor Phase Deposition(OVPD) and applied it to fabrication of Organic Thin Film Transistor(OTFT). We extracted the optimum deposition conditions such as evaporation temperature of $260^{\circ}C$, carrier gas flow rate of 10 sccm and chamber vacuum pressure of 0.1 torr. We fabricated 72 OTFTs on the 4 inch size Si Wafer, Which produced the average mobility of $0.1{\pm}0.021cm^2/V{\cdot}s$, average subthreshold slope of 1.04 dec/V, average threshold voltage of -6.55 V, and off-state current is $0.973pA/{\mu}m$. The overall performance of pentacene TFTs over 4 ' wafer exhibited the uniformity with the variation less than 20 %. This proves that OVPD is a suitable methode for the deposition of organic thin film over a large area substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.101-105
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• 2000

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.