• Progress in Superconductivity and Cryogenics
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• v.24 no.3
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• pp.47-51
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• 2022

With the innovative development of bio, pharmaceutical, and semiconductor technologies, it is essential to demand a next-generation transfer system that minimizes dust and vibrations generated during the manufacturing process. In order to develop dust-free and non-contact transfer systems, the high temperature superconductor (HTS) bulks have been applied as a magnet for levitation. However, sintered HTS bulk magnets are limited in their applications due to their relatively low critical current density (J_c) of several kA/cm² and low mechanical properties as a ceramic material. In addition, during cooling to cryogenic temperatures repeatedly, cracks and damage may occur by thermal shock. On the other hand, the bulk magnets made by stacked HTS tapes have various advantages, such as relatively high mechanical properties by alternate stacking of the metal and ceramic layer, high magnetic levitation performance by using coated conductors with high J_c of several MA/cm², consistent superconducting properties, miniaturization, light-weight, etc. In this study, we tried to fabricate HTS tapes stacked bulk magnets with 60 mm × 60 mm area and various numbers of HTS tape stacked layers for magnetic levitation. In order to examine the levitation forces of bulk magnets stacked with HTS tapes from 1 to 16 layers, specialized force measurement apparatus was made and adapted to measure the levitation force. By increasing the number of HTS tapes stacked layers, the levitation force of bulk magnet become larger. 16 HTS tapes stacked bulk magnets show promising levitation force of about 23.5 N, 6.538 kPa at 10 mm of levitated distance from NdFeB permanent magnet.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.108-108
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• 1999

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Journal of KIISE
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• v.44 no.1
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• pp.36-43
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• 2017

Syntactic information represents the dependency relation between predicates and arguments, and it is helpful for improving the performance of Semantic Role Labeling systems. However, syntax analysis can cause computational overhead and inherit incorrect syntactic information. To solve this problem, we exclude syntactic information and use only morpheme information to construct Semantic Role Labeling systems. In this study, we propose an end-to-end SRL system that only uses morpheme information with Stacked Bidirectional LSTM-CRFs model by extending the LSTM RNN that is suitable for sequence labeling problem. Our experimental results show that our proposed model has better performance, as compare to other models.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Journal of Sensor Science and Technology
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• v.22 no.4
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.10
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• pp.3211-3229
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• 2022

To solve the problems existing in the process of Weibo disaster rumor recognition, such as lack of corpus, poor text standardization, difficult to learn semantic information, and simple semantic features of disaster rumor text, this paper takes Sina Weibo as the data source, constructs a dataset for Weibo disaster rumor recognition, and proposes a deep learning model BERT_AT_Stacked LSTM for Weibo disaster rumor recognition. First, add adversarial disturbance to the embedding vector of each word to generate adversarial samples to enhance the features of rumor text, and carry out adversarial training to solve the problem that the text features of disaster rumors are relatively single. Second, the BERT part obtains the word-level semantic information of each Weibo text and generates a hidden vector containing sentence-level feature information. Finally, the hidden complex semantic information of poorly-regulated Weibo texts is learned using a Stacked Long Short-Term Memory (Stacked LSTM) structure. The experimental results show that, compared with other comparative models, the model in this paper has more advantages in recognizing disaster rumors on Weibo, with an F1_Socre of 97.48%, and has been tested on an open general domain dataset, with an F1_Score of 94.59%, indicating that the model has better generalization.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.202-204
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• 2004

We study theoretically optical properties of thin layered stacked monochrome cholesteric liquid-crystal displays. Thin thickness of the layers (${\sim}1{\mu}m$) allows us appreciably to reduce driving voltage and use such displays in smart cards. Good selective reflection is achieved due to stacked structure. Dependence of the reflectivity of this type of displays on the quantity of the layers, their thickness, and liquid crystal birefringence is investigated.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.339-342
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• 1998

The stacked microstrip patch antenna is modeled by a simple cavity model. Using this model, the input impedance of the stacked microstrip patch antenna fed by a coaxial probe is expressed as a function of antenna paprameters and frequency. We calculate the input impedance of the stacked microstrip patch antenna for the variation of frequency.