• 한국초전도ㆍ저온공학회논문지
• /
• 제24권3호
• /
• pp.47-51
• /
• 2022

With the innovative development of bio, pharmaceutical, and semiconductor technologies, it is essential to demand a next-generation transfer system that minimizes dust and vibrations generated during the manufacturing process. In order to develop dust-free and non-contact transfer systems, the high temperature superconductor (HTS) bulks have been applied as a magnet for levitation. However, sintered HTS bulk magnets are limited in their applications due to their relatively low critical current density (J_c) of several kA/cm² and low mechanical properties as a ceramic material. In addition, during cooling to cryogenic temperatures repeatedly, cracks and damage may occur by thermal shock. On the other hand, the bulk magnets made by stacked HTS tapes have various advantages, such as relatively high mechanical properties by alternate stacking of the metal and ceramic layer, high magnetic levitation performance by using coated conductors with high J_c of several MA/cm², consistent superconducting properties, miniaturization, light-weight, etc. In this study, we tried to fabricate HTS tapes stacked bulk magnets with 60 mm × 60 mm area and various numbers of HTS tape stacked layers for magnetic levitation. In order to examine the levitation forces of bulk magnets stacked with HTS tapes from 1 to 16 layers, specialized force measurement apparatus was made and adapted to measure the levitation force. By increasing the number of HTS tapes stacked layers, the levitation force of bulk magnet become larger. 16 HTS tapes stacked bulk magnets show promising levitation force of about 23.5 N, 6.538 kPa at 10 mm of levitated distance from NdFeB permanent magnet.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 1999년도 추계학술발표강연 및 논문개요집
• /
• pp.108-108
• /
• 1999

• 마이크로전자및패키징학회지
• /
• 제30권3호
• /
• pp.40-50
• /
• 2023

최근 스마트폰의 부품 수는 급격히 증가하고 있는 반면, PCB 기판의 크기는 지속적으로 감소하고 있다. 따라서 부품의 실장밀도를 개선하기 위해 PCB를 쌓아서 올리는 stacked PCB 구조의 3D 실장 기술이 개발되어 적용되고 있다. Stacked PCB에서 PCB 간 솔더 접합 품질을 확보하는 것이 매우 중요하다. 본 연구에서는 stacked PCB의 신뢰성을 향상시키기 위하여, 인터포저(interposer) PCB 및 sub PCB의 프리프레그의 물성, PCB 두께, 층수에 대한 휨의 영향을 실험과 수치해석을 통해 분석하였다. 또한 솔더 접합부의 응력을 최소화하기 위해 인터포저 패드 설계 구조에 따른 접합강도를 분석하였다. 인터포저 PCB의 휨은 프리프레그의 열팽창계수가 적을수록 감소하였으며, 유리전이온도(Tg)가 높을수록 감소하였다. 그러나 온도가 240℃ 이상이면 휨의 개선 효과는 크지 비교적 크지 않다. 또한 FR-4 프리프레그에 비하여 FR-5을 적용할 경우에 휨은 더 감소하였으며, 프리프레그의 층수와 두께가 높을수록 휨은 감소하였다. 한편 sub PCB의 경우, 휨은 프리프레그의 Tg 보다 열팽창계수가 더 중요한 변수임을 확인하였고, 두께를 증가시키는 것이 휨 감소에 효과적이었다. 솔더 접합력을 향상시키기 위하여 다양한 인터포저 패드 디자인을 적용하여 전단력 시험을 수행한 결과, 더미 패드를 추가하면 접합강도가 증가하였다. 또한 텀블 시험 결과, 더미 패드가 없을 때의 크랙 발생율은 26.8%이며, 더미 패드가 있으면 크랙 발생율은 0.6%로 크게 감소하였다. 본 연구의 결과는 stacked PCB의 설계 가이드라인 제시를 위한 유용한 결과로 판단된다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권2호
• /
• pp.186-192
• /
• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• 정보과학회 논문지
• /
• 제44권1호
• /
• pp.36-43
• /
• 2017

의미역 결정 연구에 있어 구문 분석 정보는 술어-논항 사이의 의존 관계를 포함하고 있기 때문에 의미역 결정 성능 향상에 큰 도움이 된다. 그러나 의미역 결정 이전에 구문 분석을 수행해야 하는 비용(overhead)이 발생하게 되고, 구문 분석 단계에서 발생하는 오류를 그대로 답습하는 단점이 있다. 이러한 문제점을 해결하기 위해 본 논문에서는 구문 분석 정보를 제외한 형태소 분석 정보만을 사용하는 End-to-end SRL 방식의 한국어 의미역 결정 시스템을 제안하고, 순차 데이터 모델링에 적합한 LSTM RNN을 확장한 Stacked Bidirectional LSTM-CRFs 모델을 적용해 구문 분석 정보 없이 기존 연구보다 더 높은 성능을 얻을 수 있음을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권1호
• /
• pp.27-31
• /
• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• 센서학회지
• /
• 제22권4호
• /
• pp.256-261
• /
• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제16권10호
• /
• pp.3211-3229
• /
• 2022

To solve the problems existing in the process of Weibo disaster rumor recognition, such as lack of corpus, poor text standardization, difficult to learn semantic information, and simple semantic features of disaster rumor text, this paper takes Sina Weibo as the data source, constructs a dataset for Weibo disaster rumor recognition, and proposes a deep learning model BERT_AT_Stacked LSTM for Weibo disaster rumor recognition. First, add adversarial disturbance to the embedding vector of each word to generate adversarial samples to enhance the features of rumor text, and carry out adversarial training to solve the problem that the text features of disaster rumors are relatively single. Second, the BERT part obtains the word-level semantic information of each Weibo text and generates a hidden vector containing sentence-level feature information. Finally, the hidden complex semantic information of poorly-regulated Weibo texts is learned using a Stacked Long Short-Term Memory (Stacked LSTM) structure. The experimental results show that, compared with other comparative models, the model in this paper has more advantages in recognizing disaster rumors on Weibo, with an F1_Socre of 97.48%, and has been tested on an open general domain dataset, with an F1_Score of 94.59%, indicating that the model has better generalization.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.202-204
• /
• 2004

We study theoretically optical properties of thin layered stacked monochrome cholesteric liquid-crystal displays. Thin thickness of the layers (${\sim}1{\mu}m$) allows us appreciably to reduce driving voltage and use such displays in smart cards. Good selective reflection is achieved due to stacked structure. Dependence of the reflectivity of this type of displays on the quantity of the layers, their thickness, and liquid crystal birefringence is investigated.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.339-342
• /
• 1998

The stacked microstrip patch antenna is modeled by a simple cavity model. Using this model, the input impedance of the stacked microstrip patch antenna fed by a coaxial probe is expressed as a function of antenna paprameters and frequency. We calculate the input impedance of the stacked microstrip patch antenna for the variation of frequency.