• 한국결정성장학회지
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• 제12권3호
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• 한국진공학회지
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• 제21권1호
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• pp.29-35
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• 2012

수소화된 실리콘 질화막은 결정질 태양전지 산업에서 반사방지막과 패시베이션 층으로 널리 사용되고 있다. 또한, 수소화된 질화막은 금속 소성공정과 같은 높은 공정온도를 거친 후에도 결정질 실리콘 태양전지의 표면층으로서 충족되는 특성들이 변하지 않고 유지 되어야 한다. 본 연구에서는 Plasma enhanced chemical vapor deposition 장치를 이용한 수소화된 실리콘 질화막의 특성 변화에 대한 경향성을 알아보기 위하여 증착조건의 변수(온도, 증착거리, 무선주파수 전력, 가스비율 등)들을 다양하게 가변하여 증착조건의 최적화를 찾았다. 이후 수소화된 실리콘 질화막의 전구체가 되는 사일렌($SiH_4$)과 암모니아 ($NH_3$) 가스비를 변화시켜가며 결정질 실리콘 태양전지에 사용되기 위한 박막의 광학 전기 화학적 그리고 표면 패시베이션 특성들을 분석하였다. 가스 비율에 따른 수소화된 실리콘 질화막의 굴절율 범위는 1.90~2.20까지 나타내었다. 결정질 실리콘 태양전지에 사용하기 위한 가장 적합한 특성은 3.6 ($NH_3/SiH_4$)의 가스비율을 나타내었다. 이를 통하여 $156{\times}156mm$ 대면적 결정질 실리콘 태양전지를 제작하여 17.2 %의 변환 효율을 나타내었다.

• 전자공학회논문지A
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• 제29A권2호
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• pp.55-62
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• 1992

Polycrystalline silicon ingots were manufactured using the casting method for polycrystalline silicon solar cells. These ingots were cut into wafers and ten n$^{+}$p type solar cells were made through the following simple process` surface etching, n$^{+}$p junction formation, metalization and annealing. For the grain boundary passivation, the samples were oxidized in O$_2$ for 5 min. at 80$0^{\circ}C$ prior to diffusion in Ar for 100 min. at 95$0^{\circ}C$. The conversion efficiency of polycrystalline silicon solar cells made from these wafers showed about 70-80% of those of the single crystalline silicon solar cell and superior conversion efficiency, compared to those of commercial polycrystalline wafers of Wacker Chemie. The maximum conversion efficiency of our wafers was indicated about 8%(without AR coating) in spite of such a simple fabrication method.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2006년도 추계학술발표회 초록집
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• pp.4-5
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• 2006

This paper represents modeling and optimization techniques for solar cell process on single-crystalline float zone (FZ) wafers with high efficiency; There were the four significant processes : i)emitter formation by diffusion, anti-reflection-coating (ARC) with silicon nitride using plasma-enhanced chemical vapor deposition (PECVD); iii)screen-printing for front and back metallization; and iv)contact formation by firing. In order to increase the performance of solar cells, the contact formation process is modeled and optimized. This paper utilizes the design of experiments (DOE) in contact formation to reduce process time, fabrication costs. The experiments were designed by using central composite design which is composed of $2^4$ factorial design augmented by 8 axial points with three center points. After contact formation process, the efficiency of the solar cell is modeled using neural networks. This model is used to analyse the characteristics of the process, and to optimize the process condition using genetic algorithms (GA). Finally, find optimal recipe for solar cell efficiency.

• 한국결정성장학회지
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• 제15권2호
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• pp.45-50
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• 2005

규소 표면의 기계적 손상은 산화 공정 중에 규소 표면에 여러 가지 형태의 결함들을 발생 시킨다. 규소 표면에 손상을 주는 마모 입자가 커짐에 따라 OISF보다는 etch pit의 형상이 동굴형인 선 결함(line defects)들이 많이 발생된다. 이들 결함들은 실리콘 결정을 성장시키는 단계에서 형성되는 결함들과는 상호 관련이 없다. 방향성 응고법으로 성장된 규소 결정속에 존재하는 결함들은 주로 twin과 stacking fault들이며 응고과정에서 발생이 예상되는 응력에 의한 전위는 거의 발견되지 않았다. 따라서 Czochralski 법으로 성장된 단 결정 규소뿐 아니라 방향성 응고법으로 성장된 다 결정 규소 기판도 표면의 결함들을 이용하여 extrinsic gettering을 통한 규소 결정 내부의 불순물 제거의 가능성이 높다.

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.683-689
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• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

• 에너지공학
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• 제21권3호
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• pp.243-248
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• 2012

본 연구는 고온고습 시험을 통하여 Cell 레벨에서의 표면관찰 및 효율저하를 분석하였다. 고온고습 시험조건은 KS C IEC-61215에서 제시한 PV 모듈하의 조건을 이용하여 온도 $85^{\circ}C$, 습도 85%, 1000hr 동안 수행하였다. EL(Electroluminescence)촬영을 통하여 Cell 표면의 이상 유 무를 분석한 결과, 시간이 경과함에 따라, 부분적으로 표면이 손상되어 변색되는 것을 확인하였다. 고온고습 시험 전 단결정 Cell 및 다결정 Cell의 효율은 각각 17.7%, 15.5%였으며, 1000hr 수행 후 15.6%, 14.0%로 각각 11.9%와 9.3%의 감소율을 보였다. 또한, 경년 시 나타나는 전기적 특성을 분석하기 위하여 FF(Fill Factor)값을 분석한 결과, 고온고습 시험 후 단결정 Cell은 78.7%에서 75.0%로 4.7%, 다결정 Cell은 78.1%에서 76.7%로 1.8%의 감소율을 보였다. 태양전지 실리콘의 원자배열 및 순도에 따라 효율 변화에 영향을 받아 단결정 Cell이 다결정 Cell보다 효율저하가 크게 나타났다고 판단된다. 또한, FF감소율보다 효율 감소율이 크게 저하된 것을 확인할 수 있었으며, 이는 Cell의 외부환경적 요인에 의한 표면 손상이 p-n접합층 접촉저항과 경년 시 나타나는 FF 감소율보다 크게 영향을 준 것으로 판단된다.

• 한국표면공학회지
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• 제28권3호
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• pp.182-191
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• 1995

A highly porous silicon layer was fabricated by anodizing single crystalline silicon in a dilute solution of hydrofluoric acid. The color of the porous silicon changed from red and blue to yellow gold during the anodizing process. The current-voltage (I-V) curve of the anodizing process showed a typical Schottky diode rectification form. The cell voltage decreased with the increase of HF concentration in the solution at high current range. However, the voltage was independent on HF concentration in the solution at low current range. The pore size was dependant on anodizing condition (HF concentration, current and anodizing time). The pore size and wall width of porous silicon layer were 4~6 and 1~3 nm, respectively. Surface of the porous silicon was covered with silicon compound ($SiH_x$etc.) according to IR spectrum analysis. The peak wavelength and width of photoluminescence (PL) spectrum of porous silicon were 650~850 nm (1.5~1.9 eV) and 250 nm, respectively. The photoluminescence intensity and peak wavelength, and porosity of porous silicon increased with increasing anodizing current and decreased with increasing HF concentration in the anodizing solution.

• 한국레이저가공학회지
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• 제14권4호
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• pp.21-27
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• 2011

In this work, we have studied on time-resolved transient reflective image of single crystalline Si surface after single-shot fs-laser irradiation with varying the laser fluence under two different laser spot sizes. The temporal profiles of transient reflectivity changes as well as its maximum values at the early delay time were found to be strongly dependent on both the laser beam spot size and laser fluence. We have interpreted the dependence of transient reflectivity changes on the laser spot size in terms of a relaxation of the generated free carriers to the bulk silicon, which should be interacted with the plasma.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.1001-1003
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• 1998

In this paper, $Ar^+$ ion laser etching process of single/poly crystalline silicon with $CCl_{2}F_{2}$ gas is studied for MEMS applications. To investigate the effects of process parameters, laser power, gas pressure, scanning speed were varied and multiple scanning was carried out to obtain high aspect ratio. In addition, scanning width was varied to observe the trench profile etched in repeating scanning cycle. From the etching of $2.6{\mu}m$ thick polycrystalline Si deposited on insulator, trench with flat bottom and vertical side wall was obtained and it is possible to apply this results for MEMS applications.