• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.773-779
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• 2013

We propose an efficient method to measure a pulse width using multiphase clock signals generated from a ring oscillator. These clocks, which have the same frequency and are evenly spaced, give multiple rising edges within a clock cycle. Thus, it is possible to measure a pulse width more accurately than with existing single clock-based methods. The proposed method is applied to a capacitive touch switch. Experimental results show that the capacitive touch switch with the proposed method gives a 118 fF resolution, which is 6.4 times higher than that of the touch switch with a single clock-based pulse width measurement method.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.394-397
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• 2003

In this paper, we have proposed a clock recovery algorithm of OFDM/QPSK-DMR(Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio)system using BL-PSF(Band Limited-Pulse Shaping Filter) and have analyzed the clock phase error variance performance of OFDM/QPSK and single carrier DMR systems. The existing OFDM/QPSK-DMR system using the windowing requires training sequence or CP(Cyclic Prefix) to synchronize a receiver clock frequency Because there is no training sequence or CP(Cyclic prefix) in our proposed DMR system, the proposed clock recovery algorithm is useful to the OFDM/QPSK-DMR system using BL-PSF, The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DMR system under AWGN(Additive White Gaussian Noise) environment.

• Genomics & Informatics
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• v.18 no.4
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• pp.38.1-38.9
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• 2020

Chronotype is an important moderator of psychiatric illnesses, which seems to be controlled in some part by genetic factors. Clock genes are the most relevant genes for chronotype. In addition to the roles of individual genes, gene-gene interactions of clock genes substantially contribute to chronotype. We investigated genetic associations and gene-gene interactions of the clock genes BHLHB2, CLOCK, CSNK1E, NR1D1, PER1, PER2, PER3, and TIMELESS for chronotype in 1,293 healthy Korean individuals. Regression analysis was conducted to find associations between single nucleotide polymorphism (SNP) and chronotype. For gene-gene interaction analyses, the quantitative multifactor dimensionality reduction (QMDR) method, a nonparametric model-free method for quantitative phenotypes, were performed. No individual SNP or haplotype showed a significant association with chronotype by both regression analysis and single-locus model of QMDR. QMDR analysis identified NR1D1 rs2314339 and TIMELESS rs4630333 as the best SNP pairs among two-locus interaction models associated with chronotype (cross-validation consistency [CVC] = 8/10, p = 0.041). For the three-locus interaction model, the SNP combination of NR1D1 rs2314339, TIMELESS rs4630333, and PER3 rs228669 showed the best results (CVC = 4/10, p < 0.001). However, because the mean differences between genotype combinations were minor, the clinical roles of clock gene interactions are unlikely to be critical.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.245-249
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• 2004

In this paper, we have proposed a clock recovery algorithm of Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio(OFDM/QPSK-DMR) system using Band Limited-Pulse Shaping Filter(BL-PSF) and compared the clock phase error variance of OFDM/QPSK-DMR system with that of single carrier DMR system. The OFDM/QPSK-DMR system using windowing method requires training sequence or Cyclic Prefix (CP) to synchronize the clock phase of received signal. But transmit efficient is increased in our proposed DMR system because of no using redundant data such as training sequence or CP. The proposed clock recovery algorithm is simply realized in the OFDM/QPSK-DMR system using BL-PSF. The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DR system under Additive White Gaussian Noise(AWGN) environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.