• International Journal of Control, Automation, and Systems
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• v.3 no.spc2
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• pp.322-333
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• 2005

This paper proposes a combination of the Thyristor Controlled Series Capacitor (TCSC) and Static Var Compensator (SVC) installation for enhancing the damping performance of a power system. The developed scheme employs a damping controller which coordinates measurement signals with control signals to control the TCSC and SVC. The coordinated control method is based on the application of projective controls. Controller performance over a range of operating conditions is investigated through simulation studies on a single-machine infinite-bus power system. The linear analysis and nonlinear simulation results show that the proposed controller can significantly improve the damping performance of the power system and hence, increase its power transfer capabilities. In this paper, a current injection model of TCSC is developed and incorporated in the transmission system model. By using equivalent injected currents at terminal buses to simulate a TCSC no modification of the bus admittance matrix is required at each iteration.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.6
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• pp.259-265
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• 2000

The purpose of this paper is to detect and identify topological errors in order to maintain a reliable database for the state estimator. In this paper, a two stage estimation procedure is used to identify the topology errors. At the first stage, the WSAV state estimator which has characteristics to remove bad data during the estimation procedure is run for finding out the suspected branches at which topology errors take place. The resulting residuals are normalized and the measurements with significant normalized residuals are selected. A set of suspected branches is formed based on these selected measurements; if the selected measurement is a line flow, the corresponding branch is suspected; if it is an injection, then all the branches connecting the injection bus to its immediate neighbors are suspected. A new WLAV state estimator adding the branch flow errors in the state vector is developed to identify the branch topology errors. Sample cases of single topology error and topology error with a measurement error are applied to IEEE 14 bus test system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.1947-1955
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• 1989

With the increasing complexity of cabling at sensory level in process control and manufacturing automation, field buses were introduced to replace the traditional point to point links from each sensor or acruator to its controlling equipments by a single link on which all information is transmitted seriall and multiplexed in time. In this papr, we introduce the BITBUS network as a field bus. For the service discipline of the BITBUS network, two service strategies are proposed to obtain the performance of the network. They are the equal priority cyclic service strategy and the non-equal priority cyclic service strategy. The former assigns equal priority to each node for polling and the latter assumes non-equal priority. The BITBUS network was modeled as a cyclic queueing model and it is analyzed by two methods: the Kuehn's and the Boxma's. Computer simulation was also done for the cyclic queueing model and simulation results were compared with those. Under mathematically non-analyzable environment, only the computer simulation was done. From the simulation result, in order to meet the response time requirement of 5 msec imposed by International Electrotechnical Commission when each node has the average traffic of 5000 messages/sec in manufacturing automation the number of slave nodes should be smaller than 10 at the transmission rate of 2.5 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1921-1929
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• 1997

This paper describes a direct transmission method of multimedia data stream between a multimedia data processor and a communication interface without using system memory. I propose the direct transfer method of multimedia data through the single data path, without additional data path between a multimedia data processor and a communication interface in multimedia platforms. The hardware architecture and functions for the direct transfer method is defined. Procedure to transfer multimedia data to and from the multimedia data processor is described by means of control flow chart. Comparing the proposed method with general methods, I show that the proposed method can decrease number of bus accesses and bus cycles.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.423-432
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• 2014

Non-dominated Sorting Genetic Algorithm-II (NSGA-II) is applied for solving Combined Economic Emission Dispatch (CEED) problem with valve-point loading of thermal generators. This CEED problem with valve-point loading is a nonlinear, constrained multi-objective optimization problem, with power balance and generator capacity constraints. The valve-point loading introduce ripples in the input-output characteristics of generating units and make the CEED problem as a nonsmooth optimization problem. To validate its effectiveness of NSGA-II, two benchmark test systems, IEEE 30-bus and IEEE 118-bus systems are considered. To compare the Pareto-front obtained using NSGA-II, reference Pareto-front is generated using multiple runs of Real Coded Genetic Algorithm (RCGA) with weighted sum of objectives. Comparison with other optimization techniques showed the superiority of the NSGA-II approach and confirmed its potential for solving the CEED problem. Numerical results show that NSGA-II algorithm can provide Pareto-front in a single run with good diversity and convergence. An approach based on Technique for Ordering Preferences by Similarity to Ideal Solution (TOPSIS) is applied on non-dominated solutions obtained to determine Best Compromise Solution (BCS).

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.236-241
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• 2017

This paper presents a single-phase grid connected voltage-ed inverter with a power decoupling circuit. In the single-phase grid connected voltage-ed inverter, it is well known that a power pulsation with twice the grid frequency is contained in the input power. In a conventional voltage type inverter, electrolytic capacitors with large capacitance have been used in order to smooth the DC voltage. However, lifetime of those capacitors is shortened by the power pulsation with twice grid frequency. The authors have been studied a active power decoupling(APD) method that reduce the pulsating power on the input DC bus line, this enables to transfer the ripple energy appeared on the input DC capacitors into the energy in a small film capacitor on the additional circuit. Hence, extension of the lifetime of the inverter can be expected because the small film capacitor substitutes for the large electrolytic capacitors. Finally, simulation and experimental results are discussed.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.467-475
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• 2009

Congestion management is one of the technical challenges in power system deregulation. This paper presents single objective and multi-objective optimization approaches for optimal choice, location and size of Static Var Compensators (SVC) and Thyristor Controlled Series Capacitors (TCSC) in deregulated power system to improve branch loading (minimize congestion), improve voltage stability and reduce line losses. Though FACTS controllers offer many advantages, their installation cost is very high. Hence Independent System Operator (ISO) has to locate them optimally to satisfy a desired objective. This paper presents optimal location of FACTS controllers considering branch loading (BL), voltage stability (VS) and loss minimization (LM) as objectives at once using GA. It is observed that the locations that are most favorable with respect to one objective are not suitable locations with respect to other two objectives. Later these competing objectives are optimized simultaneously considering two and three objectives at a time using multi-objective Strength Pareto Evolutionary Algorithms (SPEA). The developed algorithms are tested on IEEE 30 bus system. Various cases like i) uniform line loading ii) line outage iii) bilateral and multilateral transactions between source and sink nodes have been considered to create congestion in the system. The developed algorithms show effective locations for all the cases considered for both single and multiobjective optimization studies.

• Advances in Energy Research
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• v.4 no.4
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• pp.255-274
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• 2016

This paper presents a novel symbiotic organisms search (SOS) algorithm to optimize both real power loss (RPL) and voltage stability limit (VSL) of a transmission network by controlling the variables such as unified power flow controller (UPFC) location, UPFC series injected voltage magnitude and phase angle and transformer taps simultaneously. Mathematically, this issue can be formulated as nonlinear equality and inequality constrained multi objective, multi variable optimization problem with a fitness function integrating both RPL and VSL. The symbiotic organisms search (SOS) algorithm is a nature inspired optimization method based on the biological interactions between the organisms in ecosystem. The advantage of SOS algorithm is that it requires a few control parameters compared to other meta-heuristic algorithms. The proposed SOS algorithm is applied for solving optimum control variables for both single objective and multi-objective optimization problems and tested on New England 39 bus test system. In the single objective optimization problem only RPL minimization is considered. The simulation results of the proposed algorithm have been compared with the results of the algorithms like interior point successive linear programming (IPSLP) and bacteria foraging algorithm (BFA) reported in the literature. The comparison results confirm the efficacy and superiority of the proposed method in optimizing both single and multi objective problems.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.319-328
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• 2020

The recent use of distributed power generation systems constructed with DC-DC converters has become extremely popular owing to the rising need for environment friendly energy generation power systems. In this study, a new single-phase five-level inverter for off-grid applications constructed with a multilevel DC-DC step-up converter is proposed to boost a low-level DC voltage (36 V-64 V) to a high-level DC bus (380 V) and invert and connect them with a single-phase 230 V rms AC load. Compared with other traditional multilevel inverters, the proposed five-level inverter has a reduced number of switching devices, can generate high-quality power with lower THD values, and has balanced voltage stress for DC capacitors. Moreover, the proposed topology does not require multiple DC sources. Finally, the performance of the proposed topology is presented through the simulation and experimental results of a 400 W hardware prototype.