• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.44-52
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• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1190-1199
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• 2016

This study proposes a classification and compensation algorithm of two non-ideal output signals of a resolver to reduce position errors. Practically, a resolver generates position errors because of amplitude imbalance and quadrature imperfection between the two output signals of the resolver. In this study, a digital signal processor system based on a resolver-to-digital converter is used to reconstruct the two output signals of the resolver. The two output signals, "sin" and "cos," can be represented by a unit circle on the xy-plot. The classification and compensation of the errors can be obtained by using the radius and area of the circle made by the resolver signals. The method computes the integration of the areas made by the two resolver output signals to classify and compensate the error. This system cannot be applied during transient response given that the area integration during the transient state causes an error in the proposed method. The proposed method does not need any additional hardware. The experimental results verify the effectiveness of the proposed algorithm.