• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.232.2-232.2
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• 2014

Since its discovery in 2004, graphene, a sp2-hybridized 2-Dimension carbon material, has drawn enormous attention. A variety of approaches have been attempted, such as epitaxial growth from silicon carbide, chemical reduction of graphene oxide and CVD. Among these approaches, the CVD process takes great attention due to its guarantee of high quality and large scale with high yield on various transition metals. After synthesis of graphene on metal substrate, the subsequent transfer process is needed to transfer graphene onto various target substrates, such as bubbling transfer, renewable epoxy transfer and wet etching transfer. However, those transfer processes are hard to control and inevitably induce defects to graphene film. Especially for wet etching transfer, the metal substrate is totally etched away, which is horrendous resources wasting, time consuming, and unsuitable for industry production. Thus, our group develops one-step process to directly grow graphene on glass substrate in plasma enhanced chemical vapor deposition (PECVD). Copper foil is used as catalyst to enhance the growth of graphene, as well as a temperature shield to provide relatively low temperature to glass substrate. The effect of growth time is reported that longer growth time will provide lower sheet resistance and higher VSG flakes. The VSG with conductivity of $800{\Omega}/sq$ and thickness of 270 nm grown on glass substrate can be obtained under 12 min growing time. The morphology is clearly showed by SEM image and Raman spectra that VSG film is composed of base layer of amorphous carbon and vertically arranged graphene flakes.

• Korean Journal of Materials Research
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• v.17 no.11
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• pp.618-621
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• 2007

Chromium nitride (CrN) films were deposited on silicon substrate by RF magnetron sputtering assisted by inductive coupled nitrogen plasma without intentional substrate heating. Films were deposited with different levels of bombarding energy by nitrogen ions $(N^+)$ to investigate the influence of substrate bias voltage $(V_b)$ on the growth of CrN thin films. XRD spectra showed that the crystallographic structure of CrN films was strongly affected by substrate bias voltage. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) results showed that surface roughness and grain size of the CrN films varied significantly with bias voltage. For - 80 $V_b$ depositions, the CrN films showed bigger grain sizes than those of other bias voltage conditions. The lowest surface roughness of 0.15 nm was obtained from the CrN films deposited at .130 $V_b$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.481-485
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• 2003

Amorphous silicon (a-Si:H) based TFT process has been studied at the maximum temperature of 15$0^{\circ}C$ with 25${\mu}{\textrm}{m}$ thick flexible and adhesive tape type polyimide foil substrate, which has benefit on handling a rugged, flexible plastic substrate trough sticking simply it to glass. This paper summarize the process procedure of the TFT on the plastic substrate and shows its electrical characteristics in comparison with glass substrate using primarily the ON/OFF current ratio and the field effect mobility as the quality criterion. The a-SiN:H coating layer played an important role in decreasing surface roughness of plastic substrate, so leakage current of TFT was decreased and mobility was increased. The results show that high quality a-Si:H TFTs can be fabricated on the plastic substrates through coating a rough plastic surface with a-SiN:H.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.840-846
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• 1991

In case of the rapid thermal process by halogen lamps, an optical pyrometer is generally used to measure the temperature. It is, however, necessary to measure the temperature by the thermocouple when the process temperature is lower than 700$^{\circ}C$ and the correction of the temperature is required. Contact by the PdAg paste is commonly used out but in this case it is impossible to see the effect of surface states of the substrate, which is critical in the rapid thermal process. In this study, real temperature ramping speed of silicon substrates coveredwith various thin films such as SiO$_2$2, Si$_{3}N_{4}$, dopants, and conductive layers (Ti or Co) was investigated by a mechanical contact of the thermocouple. And the results were compared with the case in which the contact was made by the PdAg paste. Effect of process ambient was also studied. It was found that depending on the surface state, overshoot more than 100$^{\circ}C$ could occur. It was also found that in case of the substrate covered with conductive layers, mechanical contact might render the correct temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.828-830
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• 2000

Various substrates were compared for the investigation of the optical properties of ZnO thin films. ZnO thin films have been deposited on (100) p-type silicon substrates and (001) sapphire substrates by pulsed laser deposition technique using a Nd:YAG laser with the wavelength of 355 nm. Oxygen and nitrogen gases were used as ambient gases. Substrate temperatures were varied in the range of 200$^{\circ}C$ to 600$^{\circ}C$ at a fixed ambient gas pressure of 350 mTorr. ZnO films have been deposited on various substrates, such as Si and sapphire wafers. We have investigated substrate effect on the optical and structural properties of ZnO thin films using X-ray diffraction (XRD) and photoluminescence (PL).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• Journal of the Korean Ceramic Society
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• v.34 no.12
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• pp.1268-1274
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• 1997

Effect of elastic/plastic mismatch on the fracture of Si3N4 coating in Si3N4/Si3N4 -BN bilayer was investigated by Hertzian indentation testing. A different amount of mismatch between two layers was induced by different BN addition in the substrate layer, and Hertizian cracks were induced by using WC ball indenter. As a result, as the elastic/plastic mismatch between coating and substrate layer increased, the coating fracture easily occurred. A bending stress induced by different elastic/plastic mismatch was main reason to cause the fracture of coating.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.40-40
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• 2010

CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.745-748
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• 2007

Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) were fabricated on a flexible metal substrate at $150\;^{\circ}C$. To increase the stability of the flexible a-Si:H TFTs, they were thermally annealed at $230\;^{\circ}C$. The field effect mobility was reduced because of the strain in a- Si:H TFT under thermal annealing.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.390-390
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• 2010

Superconducting proximity effects of Nb/Si(111) were investigated with scanning tunneling microscopy(STM) and scanning tunneling spectroscopy(STS). A highly-doped($0.002\;{\omega}{\diamondsuit}cm$) Si wafer pieces were used as substrate and Nb source was thermally evaporated onto the atomically clean silicon substrate. The temperature of the silicon sample was held at $600^{\circ}C$ during the niobium deposition. And the sample was annealed at $600^{\circ}C$ for 30 minutes additionally. Volmer-Weber growth mode is preferred in Nb/Si(111) at the sample temperature of $600^{\circ}C$. With proper temperature and annealing time, we can obtain Nb islands of lateral size larger than Nb coherence length(~38nm). And outside of the islands, bare Si($7{\times}7$) reconstructed surface is exposed due to the Volmer-Weber Growth mode. STS measurement at 5.6K showed that Nb island have BCS-like superconducting gap of about 2mV around the Fermi level and the critical temperature is calculated to be as low as 6.1K, which is lower than that of bulk niobium, 9.5K. This reduced value of superconducting energy gap indicates suppression of superconductivity in nanostructures. Moreover, the superconducting state is extended out of the Nb island, over to bare Si surface, due to the superconducting proximity effect. Spatially-resolved scanning tunneling spectroscopy(SR-STS) data taken over the inside and outside of the niobium island shows gradually reduced superconducting gap.