• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.725-726
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• 2010

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.108.2-108
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• 1998

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.11a
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.635-643
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• 2016

Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.11
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.23-29
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• 2013

Development of flexible electronic devices has primarily focused on printing technology using organic materials. However, organic-based flexible electronics have several disadvantages, including low electrical performance and long-term reliability. Therefore, we fabricated nano- and micro-thick silicon film attached to the polymer substrate using transfer printing technology to investigate the feasibility of silicon-based flexible electronic devices with high performance and high flexibility. Flexibility of the fabricated samples was investigated using bending and stretching tests. The failure bending radius of the 200 nm-thick silicon film attached on a PI substrate was 4.5 mm, and the failure stretching strain was 1.8%. The failure bending radius of the micro-thick silicon film attached on a FPCB was 2 mm, and the failure strain was 3.5%, which showed superior flexibility compared with conventional silicon material. Improved flexibility was attributed to a buffering effect of the adhesive between the silicon film and the substrate. The superior flexibility of the thin silicon film demonstrates the possibility for flexible electronic devices with high performance.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.142-147
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• 2023

This paper presents a novel design of a differential patch antenna for 60-GHz millimeter-wave applications. The design process of the back-to-back (BTB) patch antenna is based on the conventional single-patch antenna. The initial design of the BTB patch antenna (Type-I) has a patch size of 0.66 × 0.98 mm² and a substrate size of 0.99 × 1.48 mm². It has a gain of 1.83 dBi and an efficiency of 94.4% with an omni-directional radiation pattern. A 0.4 mm-thick high-resistivity silicon (HRS) is employed for the substrate of the BTB patch antenna. The proposed antenna is further analyzed to investigate the effect of substrate size and resistivity. As the substrate resistivity decreases, the gain and efficiency degrade due to the substrate loss. As the substrate (HRS) size decreases approaching the patch size, the resonant frequency increases with a higher gain and efficiency. The BTB patch antenna has optimal performances when the substrate size matches the patch size on the HRS substrate (Type-II). The antenna is redesigned to have a patch size of 0.81 × 1.18 mm² on the HRS substrate in the same size. It has an efficiency of 94.9% and a gain of 1.97 dBi at the resonant frequency of 60 GHz with an omni-directional radiation pattern. Compared to the initial design of the BTB patch antenna (Type-I), the optimal BTB patch antenna (Type-II) has a slightly higher efficiency and gain with a considerable reduction in antenna area by 34.8%.

• ETRI Journal
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• v.15 no.2
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.302-303
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• 2008

Nominally undoped (intrinsic) ZnO thin films were deposited by magnetron sputtering system with utilization of substrate bias on silicon at $450^{\circ}C$. Oxygen gas was selected as sputtering gas. The deposited thins were evaluated with X-ray diffraction (XRD) for their microstructure analysis and Hall effect in Van der Pauw configuration for their electrical property. The XRD shows that the magnitude and polarity of substrate bias significantly influence the microstructure and electrical properties.