• Title/Summary/Keyword: signal power

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Development of a Communication Protocol for a Digital Traffic Signal Controller (디지털 교통신호제어기 통신체계 개발)

  • Kim, Min-Sung;Ko, Kwang-Yong;Lee, Choul-Ki;Jeong, Jun-Ha;Heo, Nak-Won
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.12 no.3
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    • pp.1-10
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    • 2013
  • Most of the current traffic signal controller use load switches to transmit high voltage power to the signal lamps. The direct transmission of high voltage power may cause a lot of problems like leakages of electric power, obstructions of pedestrian, environmental disfigurements. To overcome these problems, the development of digital type signal controller has been trying in the various methods. Digital communication between a master controller and signal lamps is the most important part to improve control performance in the digital type controller. A communication system for the digital signal controller was developed in this study. The system bases on CAN specification, includes ID structure for most peripheral devices like loops, signal lamps, push buttons, police switches. The operability of this system verified with a software based CAN simulation tool.

A Quantitative Evaluation and Comparison of Harmonic Elimination Algorithms Based on Moving Average Filter and Delayed Signal Cancellation in Phase Synchronization Applications

  • Xiong, Liansong;Zhuo, Fang;Wang, Feng;Liu, Xiaokang;Zhu, Minghua;Yi, Hao
    • Journal of Power Electronics
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    • v.16 no.2
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    • pp.717-730
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    • 2016
  • The harmonic components of grid voltage result in oscillations of the calculated phase obtained via phase synchronization. This affects the security and stability of grid-connected converters. Moving average filter, delayed signal cancellation and their related harmonic elimination algorithms are major methods for such issues. However, all of the existing methods have their limitations in dealing with multiple harmonics issues. Furthermore, few studies have focused on a comparison and evaluation of these algorithms to achieve optimal algorithm selections in specific applications. In this paper, these algorithms are quantitatively analyzed based on the derived mathematical models. Moreover, an enhanced moving average filter and enhanced delayed signal cancellation algorithms, which are applicable for eliminating a group of selective harmonics with only one calculation block, are proposed. On this basis, both a comprehensive comparison and a quantitative evaluation of all of the aforementioned algorithms are made from several aspects, including response speed, required data storage size, sensitivity to sampling frequency, and elimination of random noise and harmonics. With the conclusions derived in this paper, better overall performance in terms of harmonic elimination can be achieved. In addition, experimental results under different conditions demonstrate the validity of this study.

Implementation of Multi-Channel Power Components Measuremen System (다채널 전력분석시스템의 구현)

  • Lee, Myung-Un;Yoo, Jae-Geun;Lee, Sang-Ick;Cho, Myung-Hyun;Choe, Gyu-Ha
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.3
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    • pp.233-238
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    • 2006
  • In order to solve power disturbances, power components measurement for both supply and demand side of power system must be implemented. This paper proposed a DSP (Digital Signal Processor)-based multi-channel (voltage 8-channel and current 10-channel) power components measurement system that simultaneously can measure and analyze power components for both supply md demand side. After voltage and current measurement accuracy revision using YOKOGAWA 2558, the developed system was tested in the field.

Development of 60KV Pulse Power Supply using IGBT Stacks (IGBT 직렬구동에 의한 60KV 펄스 전원장치 개발)

  • Ryoo, H.J.;Kim, J.S.;Rim, G.H.;Sytykh, D.;Gussev, G.I.
    • Proceedings of the KIEE Conference
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    • 2006.07b
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    • pp.917-918
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    • 2006
  • In this paper, a novel new pulse power generatorbased on IGBT stacks is proposed for pulse power application. Proposed scheme consists of series connected 9power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is importantfor series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

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Fault Diagnosis of Wind Power Converters Based on Compressed Sensing Theory and Weight Constrained AdaBoost-SVM

  • Zheng, Xiao-Xia;Peng, Peng
    • Journal of Power Electronics
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    • v.19 no.2
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    • pp.443-453
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    • 2019
  • As the core component of transmission systems, converters are very prone to failure. To improve the accuracy of fault diagnosis for wind power converters, a fault feature extraction method combined with a wavelet transform and compressed sensing theory is proposed. In addition, an improved AdaBoost-SVM is used to diagnose wind power converters. The three-phase output current signal is selected as the research object and is processed by the wavelet transform to reduce the signal noise. The wavelet approximation coefficients are dimensionality reduced to obtain measurement signals based on the theory of compressive sensing. A sparse vector is obtained by the orthogonal matching pursuit algorithm, and then the fault feature vector is extracted. The fault feature vectors are input to the improved AdaBoost-SVM classifier to realize fault diagnosis. Simulation results show that this method can effectively realize the fault diagnosis of the power transistors in converters and improve the precision of fault diagnosis.

Transmitter Beamforming and Artificial Noise with Delayed Feedback: Secrecy Rate and Power Allocation

  • Yang, Yunchuan;Wang, Wenbo;Zhao, Hui;Zhao, Long
    • Journal of Communications and Networks
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    • v.14 no.4
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    • pp.374-384
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    • 2012
  • Utilizing artificial noise (AN) is a good means to guarantee security against eavesdropping in a multi-inputmulti-output system, where the AN is designed to lie in the null space of the legitimate receiver's channel direction information (CDI). However, imperfect CDI will lead to noise leakage at the legitimate receiver and cause significant loss in the achievable secrecy rate. In this paper, we consider a delayed feedback system, and investigate the impact of delayed CDI on security by using a transmit beamforming and AN scheme. By exploiting the Gauss-Markov fading spectrum to model the feedback delay, we derive a closed-form expression of the upper bound on the secrecy rate loss, where $N_t$ = 2. For a moderate number of antennas where $N_t$ > 2, two special cases, based on the first-order statistics of the noise leakage and large number theory, are explored to approximate the respective upper bounds. In addition, to maintain a constant signal-to-interferenceplus-noise ratio degradation, we analyze the corresponding delay constraint. Furthermore, based on the obtained closed-form expression of the lower bound on the achievable secrecy rate, we investigate an optimal power allocation strategy between the information signal and the AN. The analytical and numerical results obtained based on first-order statistics can be regarded as a good approximation of the capacity that can be achieved at the legitimate receiver with a certain number of antennas, $N_t$. In addition, for a given delay, we show that optimal power allocation is not sensitive to the number of antennas in a high signal-to-noise ratio regime. The simulation results further indicate that the achievable secrecy rate with optimal power allocation can be improved significantly as compared to that with fixed power allocation. In addition, as the delay increases, the ratio of power allocated to the AN should be decreased to reduce the secrecy rate degradation.

Binary Power Amplifier with 2-Bit Sigma-Delta Modulation Method for EER Transmitter

  • Lim, Ji-Youn;Cheon, Sang-Hoon;Kim, Kyeong-Hak;Hong, Song-Cheol;Kim, Dong-Wook
    • ETRI Journal
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    • v.30 no.3
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    • pp.377-382
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    • 2008
  • A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2-bit sigma-delta (${\Sigma}{\Delta}$) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2-bit digitized envelope signals. The 2-bit ${\Sigma}{\Delta}$ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over-sampling ratio, this technique is best suited for wireless communication with high data rates.

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Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

  • Kwen, Hyeunwoo;Kim, Sang-Hwan;Lee, Jimin;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.29 no.2
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    • pp.82-88
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    • 2020
  • In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.