• Title/Summary/Keyword: shared parallel systems

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Analyzing Access Histories for Detecting First Races in Shared-memory Programs (공유메모리 프로그램의 최초경합 탐지를 위한 접근역사 분석)

  • 강문혜;김영주;전용기
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.41-50
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    • 2004
  • Detecting races is important for debugging shared-memory Parallel programs, because races result in unintended nondeterministic executions of the programs. Particularly, the first races to occur in an execution of a program must be detected because they can potentially affect other races that occur later. Previous on-the-fly techniques that detect such first races based on candidate events that are likely to participate in the first races monitor access events in order to collect the candidate events during a program execution, and try to report the races only from determining the concurrency relationships of the candidates. Such races reported in this way. however, are not guaranteed to be first races, because they are not determined by taking into account how they are affected with each other. This paper presents a new post-mortem technique that analyzes, on each nesting level, candidate events collected from an execution of a shared-memory program with nested parallelism in order to report only first races. This technique is efficient, because it guarantees that first races reported by analyzing a nesting level are the races that occur first at the level, and does not require more analyses to the higher nesting levels than the current level. The Proposed technique facilitates more practical and effective debugging than the previous techniques, because it guarantees to detect first races if candidate events are collected from an execution instance of the program with nested parallelism.

Multi-Programmed Simulation of a Shared Memory Multiprocessor System (공유메모리 다중프로세서 시스템의 다중 프로그래밍 모의실험 기법)

  • 최효진;전주식
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.194-204
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    • 2003
  • The performance of a shared memory multiprocessor system is dependent on the system software such as scheduling policy as well as hardware system. Most of existing simulators, however, do not support simulation for multi-programmed environment because they can execute only a single benchmark application at a time. We propose a multi-programmed simulation method on a program-driven simulator, which enables the concurrent executions of multiple parallel workloads contending for limited system resources. Using the proposed method, system developers can measure and analyze detailed effects of resource conflicts among the concurrent applications as well as the effects of scheduling policies on a program-driven simulator. As a result, the proposed multi-programmed simulation provides more accurate and realistic performance projection to design a multiprocessor system.

A Software VIA based PC Cluster System on SCI Network (SCI 네트워크 상의 소프트웨어 VIA기반 PC글러스터 시스템)

  • Shin, Jeong-Hee;Chung, Sang-Hwa;Park, Se-Jin
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.4
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    • pp.192-200
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    • 2002
  • The performance of a PC cluster system is limited by the use of traditional communication protocols, such as TCP/IP because these protocols are accompanied with significant software overheads. To overcome the problem, systems based on user-level interface for message passing without intervention of kernel have been developed. The VIA(Virtual Interface Architecture) is one of the representative user-level interfaces which provide low latency and high bandwidth. In this paper, a VIA system is implemented on an SCI(Scalable Coherent Interface) network based PC cluster. The system provides both message-passing and shared-memory programming environments and shows the maximum bandwidth of 84MB/s and the latency of $8{\mu}s$. The system also shows better performance in comparison with other comparable computer systems in carrying out parallel benchmark programs.

A Cascade-hybrid Recommendation Algorithm based on Collaborative Deep Learning Technique for Accuracy Improvement and Low Latency

  • Lee, Hyun-ho;Lee, Won-jin;Lee, Jae-dong
    • Journal of Korea Multimedia Society
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    • v.23 no.1
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    • pp.31-42
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    • 2020
  • During the 4th Industrial Revolution, service platforms utilizing diverse contents are emerging, and research on recommended systems that can be customized to users to provide quality service is being conducted. hybrid recommendation systems that provide high accuracy recommendations are being researched in various domains, and various filtering techniques, machine learning, and deep learning are being applied to recommended systems. However, in a recommended service environment where data must be analyzed and processed real time, the accuracy of the recommendation is important, but the computational speed is also very important. Due to high level of model complexity, a hybrid recommendation system or a Deep Learning-based recommendation system takes a long time to calculate. In this paper, a Cascade-hybrid recommended algorithm is proposed that can reduce the computational time while maintaining the accuracy of the recommendation. The proposed algorithm was designed to reduce the complexity of the model and minimize the computational speed while processing sequentially, rather than using existing weights or using a hybrid recommendation technique handled in parallel. Therefore, through the algorithms in this paper, contents can be analyzed and recommended effectively and real time through services such as SNS environments or shared economy platforms.

A bivariate extension of the two-parameter exponential distribution (위치모수를 가지는 이변량지수분포의 개발)

  • 홍연웅
    • The Korean Journal of Applied Statistics
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    • v.11 no.1
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    • pp.185-192
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    • 1998
  • A bivariate extension of the two-parameter exponential distribution is proposed as a model for certain problems in system level life testing. In particular, it applies to two-component shared parallel systems having a minimum guarantee time. Various statistical properties of the model are investigated, including maximum likelihood estimators (MLEs), modified MLEs, and unbiased estimators of the parameters and their distributions.

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Improved Parallel Loop Scheduling Algorithm on Shared Memory Systems (공유메모리 시스템에서 개선된 병렬 루프 스케쥴링 알고리즘)

  • 이영규;박두순
    • Proceedings of the Korea Multimedia Society Conference
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    • 2000.04a
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    • pp.453-457
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    • 2000
  • 병렬 시스템 환경에서 최적의 스케쥴링을 수행하기 위해서는 병렬성을 가진 iteration 들에 대해 최소의 동기화 오버헤드와 load balance 가 달성하도록 스케쥴링을 수행해야한다. 다중 프로세서들은 실행을 위하여 메모리로부터 iteration 들에 대한 chunk를 계산한 후 할당받게 된다. 이때, 각 프로세서들의 상호 배타적인 메모리 접근으로 많은 오버헤드 및 병목현상이 발생된다. 또한, 프로세서에게 할당된 chunk 내 iteration 들의 실행시간 분포가 서로 상이한 경우에는 load imbalance 의 원인이 되어 결과적으로 전체 스케쥴링에 나쁜 영향을 준다. 따라서, 최적의 스케쥴링을 수행하기 위해서 본 논문에서는 기존의 스케쥴링 방법들에서 문제점들을 도출하고 자료의 국부성과 프로세서 동족성을 고려한 개선된 병렬 루프 알고리즘을 제안하고, 성능평가를 통해 개선된 알고리즘이라는 것을 보였다.

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Estimation of Bivariate Exponential Model under Censored Data

  • Cho, Kil-Ho;Kim, Young-Il
    • Journal of the Korean Data and Information Science Society
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    • v.14 no.4
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    • pp.751-758
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    • 2003
  • We consider a life testing experiment in which several two-component shared parallel systems are put on test, and the test is terminated at a predesigned experiment time. The bivariate data obtained from such a system-level life testing can be classified into three cases: 1) the case of failed two components with known failures times, 2) the case of censored two components, and 3) the case of one censored component and the other failed component of which the failure time might be known or unknown. In this thesis, the likelihood estimators for Freund's bivariate exponential life distribution under above censoring scheme are obtained. Results of comparative studies based on Monte Carlo simulation are presented.

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Fabrication and Test of the 3.8 ㎸ Resistive SFCL Based on YBCO Films (3.8 ㎸급 7직렬 저항형 고온초전도한류기의 제작 및 시험)

  • 심정욱;김혜림;현옥배;박권배;이방욱;강종성;오일성
    • Progress in Superconductivity
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    • v.5 no.2
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    • pp.136-140
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    • 2004
  • We fabricated and tested a resistive superconducting fault current limiters (SFCL) operated at 3.8 ㎸ based on YBCO thin films. The SFCL was composed of 7 components connected in series. Each component was designed to be capable of current limiting at 600 V, and has a SiC shunt resistor ( $R_{s}$) of 40 Ω in Parallel. Short circuit tests were carried out fur 0 and 90 degree faults lasting fur 5 cycles. The test results showed that the 7 components were quenched simultaneously under the safe quenches and evenly shared the applied voltage. The SFCL successfully suppressed the fault currents below 94 $A_{peak}$ within the quarter cycle after fault.t.t.

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Estimation of Freund Model for System Level Life Testing Using Component Life Data (체계수명시험에서 얻어진 부품의 수명자료를 이용한 Freund 모형의 추정)

  • 홍연웅
    • Journal of Korean Society for Quality Management
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    • v.26 no.2
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    • pp.27-38
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    • 1998
  • Consider a life testing experiment in which multiple two-component shared parallel systems are put on test, and the test is terminated at a specified number of system failures. The bivariate data obtained from such a system-level life testing can be classified into three classes: 1) the case of failed two components with known failure times, 2) the case of censored two components, and 3) the case of one censored component and the other failed component of which the failure time might be known or unknown. Under this censoring scheme and the assumption of Freund's bivariate exponential life distribution, the maximum likelihood estimators are obtained. Results of comparative studies based on Monte Carlo simulation are presented.

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Design of General -Purpose Bitonic Sorting Algorithms with a Fixed Number of Processors for Shared-Memory Parallel Computers (공유 메모리 병렬 컴퓨터 환경에서 한정된 수의 프로세서를 사용한 범용 Bitonic sorting 알고리즘의 설계)

  • Lee, Jae-Dong
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.1
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    • pp.33-42
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    • 1999
  • 지금까지의 bitonic sorting 에 대한 연구는 N 개의 key를 정렬하기 위해서는 N/2(or N)개의 프로세서가 필요하였다. 여기서는 프로세서의 수가 정렬하고자 하는 key 수에 독립적이고 또한 N/2개 이하인 경우를 고려하였다. 따라서 본 연구에서는 공유 메모리 병렬 컴퓨터 환경에서 N 개의 Key를 고정도니 수의 프로세서를 사용하여 O(log2N) 시간에 정렬 할 수 있는 두 종류의 범용 bitonic sorting 알고리즘을 구현하였다. 첫째로, VITURAL-GPBS 알고리즘은 하나의 프로세서를 사용하여 여러 개의 프로세서가 하는 역할을 모방하므로써 정렬을 수행하도록 하였다. 둘째로, VIRTUAL-GPBS 알고리즘보다 좀 더 효율적이고 빠른 FAST-GPBS 알고리즘을 소개하였다. 두 알고리즘의 주요 차이점은 FAST-GPBS 알고리즘에서는 각각의 프로세서에 배정된 여러 개의 key를 각 프로세서 내에서 가장 빠른 순차 정렬 알고리즘을 사용하면서 먼저 지역적으로 정렬을 함으로써 VIRTUAL-GPBS 보다 효율이 50% 이상 향상된 정렬을 수행할 수 있도록 하였다. FAST-GPBS 알고리즘은 compare-exchange 대신 merge-split 작업을 함으로써 컴퓨터의 사용 효율을 향상시킬 수 있다.