• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1261-1267
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• 2009

The Direct Torque Control[DTC] controls torque and flux by restricting the flux and torque errors within respective hysteresis bands, and motor torque and flux are controlled by the stator voltage space vector using optimum inverter switching table. And the Current Error Compensation method is on the basis of compensating current difference between the induction motor and its numerical model, in which the identical stator voltage is supplied for both the actual motor and the model so that the gaps between stator currents of the two can be forced to decay to zero as time proceeds. Consequently, the rotor speed approaches to the model speed, namely, setting value and the system can control motor speed precisely. This paper proposes a new sensorless speed control of induction motor using DTC and Current Error Compensation, which requires neither shaft encoder, speed estimator nor PI controllers. And through computer simulation, confirm effectiveness of proposed method.

• The Journal of Asian Finance, Economics and Business
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• v.8 no.3
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• pp.751-761
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• 2021

The Vietnamese economy is a developing country that has brought many opportunities and challenges for the banking system. Commercial banks have developed strongly from quality to quantity, which plays a vital role in developing the economy. They play an important role in capital formation, which is essential for the economic development of a country. They provide financial services to the general public and businesses, ensuring economic and social stability and sustainable growth of the economy. Therefore, the relationship between bank depth and economic growth is of importance in research. This paper used a VAR (Vector Autoregressive Models) estimator for time series data models. The data is collected quarterly from the first quarter of the year 2000 to 2020. The study uses the VAR model to examine the causal relationships of economic growth, growth in money supply expansion, private sector capital requirement, and banks' domestic credit. The results indicate a general short-run relationship between banking sector depth and economic growth with a positive connection, but in the long term, the relationship between these variables can be reversed because of other macro factors. The findings show the two-way causal relationship between GDP growth and banking depth factors. This research contributes to policy-making by underlining the banking sector depth determinants when setting regulations and policies to develop the banking sector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.