• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• Annual Conference of KIPS
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• 2003.05b
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• pp.927-930
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• 2003

Automated sequencer로부터 얻게된 서열은 PCR이나 sequencing의 영향 등으로 기존의 자료 또는 분자생물학자가 원하는 서열과는 조금씩 차이점을 나타내게 되고, 이를 보정하기 위해 수작업으로 처리하게 된다. 이는 아주 간단함 작업임에도 불구하고 30분에서 1시간, 많게는 몇 시간씩 걸리는 불편함을 감수하고 있다. 본 논문에서는 분자 생물학자들이 효율적으로 서열을 분석하게 하는 sequence finishing program의 구현에 관하여 논의하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.55-61
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• 2010

When we design the control system used Programmable Logic Controller(PLC) by Sequential Function Chart(SFC), if we use a SFC, it is easy to know the sequential flow of control, to maintenance the controller and to describe a program. We program a SFC by a unique sequence, an alternative sequence and a parallel sequence. If we program a SFC by a alternative sequence, the memory size of a alternative sequence must be larger than the memory size of a unique sequence. Therefore this thesis show an efficient method to reduce a memory size and we confirmed its feasibility through actual example.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.351-357
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• 2003

An easy learning elevator originated is opened to compare the existed teaming equipment, and it had a high studied efficiency that the sequence control circuit can open and close with the wire. The structure of equipment to be controlled from the first floor to the fifth floors is demostrated by the constructive apparatus with the lamps to express the function of the open-close of the door according to the cage moving with a mechanical actuation of the forward reverse breaker and the motor of load, and the mechanical actuation of hand-operation control components of push-button S/W and L/S and relay etc. These components let connect each other in order to control of the elevator function with the auto program and the designed sequence control circuit. Consequently the cage could go and come till 1∼5 steps with an auto program of the elevator and the sequence control circuit. The sequence control circuit is controlled by the step of forward and reverse to follow as that the sensor function of L/S1 ∼ L/S5 let posit with the control switchs of S/W1 ∼ S/W5 of PLC testing panel and switchs of S/W1 ∼ S/W5 installed on the transparent acryl plate of the frame. In here, improved apparatus is the hand-auto operation combined learning equipment to study the principle and technique of the originate sequence control circuit and the auto program of PLC.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Physical Therapy Rehabilitation Science
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• v.8 no.4
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• pp.225-233
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• 2019

Objective: The purpose of this study was to examine the possible effects of incorporating short-term slow-abdominal respiration (SAR) into an exercise program, on balance and the cardiac-related autonomic nervous system (ANS). Design: Cross-over repeated measures design. Methods: Fifteen young and healthy adults were randomly assigned into two groups (7 in the C-R group, 8 in the R-C group), each of which carried out both control sequence (C) and respiration-experiment sequence (R) in the inverse order. In the C sequence, the subjects performed passive exercises and a general exercise program (P-GEP). In the R sequence, the subjects received a short-term SAR training session and then performed the respiration incorporated general exercises program (R-RGEP). Before and after both C and R sequences, the length and the area of the displacement of the center of pressure (COP) and heart rate variability parameters were measured. Results: The total length of the COP displacement in the left single-leg-standing condition showed a significantly greater reduction after R-RGEP in the respiration-experiment sequence than after the P-GEP in the control sequence (p<0.05). The mean heart rate was significantly reduced only after R-RGEP in the respiration-experiment sequence (p<0.05) Conclusions: The slow-abdominal-respiration, trained in a simple manner and integrated into the exercise program in a single session, showed partially positive immediate effects on balance stabilization. The decrease in heart rate indicated possible involvement of the parasympathetic ANS activation in the stability, although it is not enough to decide whether it is purely due to the controlled respiration.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2005.09a
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• pp.63-68
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• 2005

Transcription factors regulate gene expression by binding to gene upstream region. Each transcription factor has the specific binding site in promoter region. So the analysis of gene upstream sequence is necessary for understanding regulatory mechanism of genes, under a plausible idea that assumption that DNA sequence motif profiles are closely related to gene expression behaviors of the corresponding genes. Here, we present an effective approach to the analysis of the relation between gene expression profiles and gene upstream sequences on the basis of kernel canonical correlation analysis (kernel CCA). Kernel CCA is a useful method for finding relationships underlying between two different data sets. In the application to a yeast cell cycle data set, it is shown that gene upstream sequence profile is closely related to gene expression patterns in terms of canonical correlation scores. By the further analysis of the contributing values or weights of sequence motifs in the construction of a pair of sequence motif profiles and expression profiles, we show that the proposed method can identify significant DNA sequence motifs involved with some specific gene expression patterns, including some well known motifs and those putative, in the process of the yeast cell cycle.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.107-112
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• 2010

When we design the control system used Programmable Logic controller(PLC), if we program a Sequential Function Chart(SFC), It is easy to understand the sequential flow of control, to maintenance the controller and to describe a program. SFC language is programmed by a single sequence, a select sequence and a parallel sequence. In a select sequence, when the select step is error, the whole process is stopped. If the error step has no connection the whole process, the loss is down when we debugging the program without stopping the whole process. Therefore, this thesis shows the efficient method of remote control for select sequence and we confirmed its feasibility through actual example.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1107-1112
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• 2002

An easy elevator originated is an opened system to compare an existing equipment, and learning efficient is high as a wiring that the sequence control circuit is on and off. The structure of an equipment to be controled from the first floor to the fifth floor is constructed by a lamp to express the function of the open-close of the door according to the cage moving, to express the mechanical actuation of the forward-reverse break and motor of load and of hand-worked control component of Push-Button S/W, L/S and Relay. In order to act of the elevator function that these components connected, designed the auto program and the sequence control circuit. Consequently the process that these(1~5steps) operated the cage with an auto program of the elevator and the sequence control circuit is controled by the step of forward and reverse that the L/S1~L/S5 of sensor adjust function let posit, by the adjustable S/W1~S/W5 of PLC testing panel and the S/W1~S/W5 which installed on the transparent acryl plate of a frame. In here, improved apparatus is the learning equipment of combined use to study the principle and the technique of the originated sequence control circuit and the auto program of PLC.