• Title/Summary/Keyword: semiconductor optimization

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A Study on Thermal Conduction Analysis for Optimization of Temperature of Coolant Heater (냉각수 가열장치의 온도 최적화를 위한 열전도 해석에 관한 연구)

  • Han, Dae Seong;Bae, Gyu Hyun
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.1
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    • pp.33-38
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    • 2022
  • This study investigates the outlet temperature of coolant heater based on heat and flow volume conditions. Through computer simulation, the coolant temperature at the outlet was analyzed to investigate the heat and flow volume conditions of the coolant heater, and the optimal conditions were derived. Results show that heat and flow volume conditions, it was confirmed that heat condition is 0.424 W/mm3, and flow volume condition is 500 l/h, demonstrates optimal conditions. The results of this study can be utilized to efficiently control the coolant temperature through various heat and flow volume conditions.

A robust controller design for rapid thermal processing in semiconductor manufacturing

  • Choi, Byung-Wook;Choi, Seong-Gyu;Kim, Dong-Sung;Park, Jae-Hong
    • 제어로봇시스템학회:학술대회논문집
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    • 1995.10a
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    • pp.79-82
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    • 1995
  • The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

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Structures of Ultrathin Copper Nanowires Encapsulated in Carbon Nanotubes (탄소나노튜브 속에 성장된 구리 나노와이어의 구조)

  • Choi, Won-Young;Kang, Jeong-Won;Song, Ki-Oh;Hwnang, Ho-Jung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.294-299
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    • 2003
  • We have investigated the structures of copper nanowires encapsulated in carbon nanotubes using a structural optimization process applied to the steepest descent method. The results showed that the stable morphology of the cylindrical ultrathin copper nanowires in carbon nanotubes is multishell packs consisted of coaxial cylindrical shells. As the diameter of copper nanotubes increased, the encapsulated copper nanowires have the face centered cubic structure as the bulk. Both the semiclassical orbits in a circle and the circular rolling of a triangular network can explain the structures of ultrathin multishell copper nanowires encapsulated in carbon nanotubes.

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Design Parameter Optimization for Hall Sensor Application

  • Park, Chang-Sung;Cha, Gi-Ho;Kang, Hyun-Soon;Song, Chang-Sup
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.86.3-86
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    • 2001
  • Hall effect sensor using 7um, 1.7 ohm-cm or 10um, 3.5 ohm-cm Bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage in chip scale the Agilent company´s 4156C and Nano-Voltage Meter were used and the best structure in offset voltage was finally selected by using ceramic package. The patterns appear to be the quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173-365uV. Meanwhile, in ...

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Experimental Analysis and Optimization of Experimental Analysis and Optimization of $CF_4/O_2$ Plasma Etching Process Plasma Etching Process (실험계획법에 의한 $CF_4/O_2$ 플라즈마 에칭공정의 최적화에 관한 연구)

  • Choi, Man-Sung;Kim, Kwang-Sun
    • Journal of the Semiconductor & Display Technology
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    • v.8 no.4
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    • pp.1-5
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    • 2009
  • This investigation is applied Taguchi method and the analysis of variance(ANOVA) to the reactive ion etching(RIE) characteristics of $SiO_2$ film coated on a wafer with Experimental Analysis and Optimization of $CF_4/O_2$ Plasma Etching Process mixture. Plans of experiments via nine experimental runs are based on the orthogonal arrays. A $L_9$ orthogonal array was selected with factors and three levels. The three factors included etching time, RF power, gas mixture ratio. The etching rate of the film were measured as a function of those factors. In this study, the etching thickness mean and uniformity of thickness of the RIE are adopted as the quality targets of the RIE etching process. The partial factorial design of the Taguchi method provides an economical and systematic method for determining the applicable process parameters. The RIE are found to be the most significant factors in both the thickness mean and the uniformity of thickness for a RIE etching process.

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Shape Optimization of PMLSM Stator for Reduce Thrust Ripple Components Using DOE (DOE 활용 추력리플성분 저감을 위한 PMLSM 고정자 형상 최적화)

  • Kwon, Jun Hwan;Kim, Jae Kyung;Jeon, Euy Sik
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.4
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    • pp.38-43
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    • 2021
  • Permanent magnet linear synchronous motor (PMLSM) is suitable for use in cleanroom environments and have advantages such as high speed, high thrust, and high precision. If the stators are arranged in the entire moving path of the mover, there is a problem in that the installation cost increases. To solve this problem, discontinuous armature arrangement PMLSM has been proposed. In this case, the mover receives a greater detent force in the section where the stator is not arranged. When a large detent force occurs, it appears as a ripple component of the thrust during PMLSM operation. If the shape of the stator is changed to reduce the detent force, the characteristics of the back EMF are changed. Therefore, in this paper, the detent force and the harmonic components of back EMF were reduced through multi-purpose shape optimization. To this end, the FEA model was constructed and main effect analysis was performed on the major shape variables affecting each objective function. Then, the optimal shape that minimizes the objective function was derived through the response surface analysis method.

SEG Applications for Semiconductor Devices (선택적 단결정 실리콘 성장의 반도체 소자 적용)

  • Cheong, Woo-Seok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.9-10
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    • 2005
  • Process diagrams of selective epitaxial growth of silicon(SEG) could be developed from CVD thermodynamics. They could not only be helpful with understanding of the mechanism, but also offer good processing guidelines in manufacturing high density devices. Through the process optimization skill, applications of SEG to high-density device structures could be possible without problems such as loading effect and facet generation, with producing outstanding electronic properties.

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Study on optimization of CMP Conditioning (CMP Conditioning 최적화에 관한 연구)

  • Han, Sang-Yeob;Yun, Seong-Kyu;Yoon, Bo-Un;Hong, Chang-Ki;Cho, Han-Ku;Moon, Joo-Tae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.51-54
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    • 2006
  • 본 연구는 CMP 공정 중의 Conditioning 최적화에 관한 내용이다. CMP Pad Conditioner의 역할은 CMP 공정 중 Slurry 및 연마 잔유물에 의해 Pad 표면에 눈막힘 현상(Glazing)이 발생하여 Wafer의 연마속도가 급속히 저하되는 현상을 방지하여 공정의 안정성을 향상시키는 데 있다. 본 연구 중 Conditioning은 In-situ 방식으로 진행되었으며, Conditioning 비율을 Polishing Time 대비 50%만 진행하여도 연마속도 저하현상은 나타나지 않음을 확인하였다. 이로써 Pad 마모랑 감소 및 Conditioner 교체 주기연장이 가능해져, CMP 공정의 Cost를 절감할 수 있다.

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Optimization of Memristor Devices for Reservoir Computing (축적 컴퓨팅을 위한 멤리스터 소자의 최적화)

  • Kyeongwoo Park;HyeonJin Sim;HoBin Oh;Jonghwan Lee
    • Journal of the Semiconductor & Display Technology
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    • v.23 no.1
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    • pp.1-6
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    • 2024
  • Recently, artificial neural networks have been playing a crucial role and advancing across various fields. Artificial neural networks are typically categorized into feedforward neural networks and recurrent neural networks. However, feedforward neural networks are primarily used for processing static spatial patterns such as image recognition and object detection. They are not suitable for handling temporal signals. Recurrent neural networks, on the other hand, face the challenges of complex training procedures and requiring significant computational power. In this paper, we propose memristors suitable for an advanced form of recurrent neural networks called reservoir computing systems, utilizing a mask processor. Using the characteristic equations of Ti/TiOx/TaOy/Pt, Pt/TiOx/Pt, and Ag/ZnO-NW/Pt memristors, we generated current-voltage curves to verify their memristive behavior through the confirmation of hysteresis. Subsequently, we trained and inferred reservoir computing systems using these memristors with the NIST TI-46 database. Among these systems, the accuracy of the reservoir computing system based on Ti/TiOx/TaOy/Pt memristors reached 99%, confirming the Ti/TiOx/TaOy/Pt memristor structure's suitability for inferring speech recognition tasks.

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Design Optimization and Development of Linear Brushless Permanent Magnet Motor

  • Chung, Myung-Jin;Gweon, Dae-Gab
    • International Journal of Control, Automation, and Systems
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    • v.1 no.3
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    • pp.351-357
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    • 2003
  • A method of design optimization for minimization of force ripple and maximization of thrust force in a linear brushless permanent magnet motor without finite element analysis is represented. The design optimization method calculated the driving force in the function of electric and geometric parameters of a linear brushless PM motor using the sequential quadratic programming method. Using electric and geometric parameters obtained by this method, the normalized force ripple is reduced 7.7% (9.7% to 2.0%) and the thrust force is increased 12.88N (111.55N to 124.43N) compared to those not using design optimization.