• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• 조명전기설비학회논문지
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• 제27권3호
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• pp.43-49
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• 2013

Recently harmonics flowing into power system is increasing as the usage of semiconductor equipments and switching mode power equipments are increasing. Harmonics cause problems such as heat increasing and reduction in capacity of transformers, especially the harmonics flowing into a distribution transformer can lead to the lifetime reduction of transformer. In this paper, we are about to develop a device that can monitor harmonics in real-time as it is affixed to a distribution transformer. Unlike the existing expensive harmonic analysis device, a new harmonic analysis algorithm is proposed in order to implement low-cost equipment. The real-time harmonic analysis algorithm proposed in this paper allows implementation on low performance microcontrollers, thus it can monitor the harmonic in real-time as it is individually affixed to the transformer. Therefore, it would improve the reliability of the transformer and stable power system operation would be possible as it can prevent the transformer accidents in advance.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• 한국정보전자통신기술학회논문지
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• 제12권2호
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• 한국산학기술학회논문지
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• 제22권1호
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• pp.327-332
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• 2021

패키지레벨에서 반도체의 신뢰성 검사는 테스트 소켓에 반도체 칩 패키지를 탑재시킨 상태에서 테스트가 진행되며, 테스트 소켓은 기본적으로 반도체 칩 패키지의 형태에 따라서 그 모양이 결정되는 것이 일반적이다. 또한, 반도체 칩 패키지의 리드와 소켓 리드의 기계적인 접촉에 의해 테스트 장비와 연결하는 매개체의 역할을 하며, 신호전달 과정에서 신호의 손실을 최소화하여 반도체에 검사신호를 잘 전달할 수 있도록 하는 기능이 핵심이다. 본 연구에서는 이웃하고 있는 전기 전달 경로의 상호 영향성을 검사 할 수 있는 기술을 적용함으로써 수명 검사와 정밀 측정뿐만 아니라 이웃하고 있는 전기 전달 경로의 구조를 포함하여 단 한 번의 접촉을 통해 100개미만의 실리콘 테스트 소켓의 합선 테스트가 가능하도록 개발하였다. 개발된 장치의 테스트 결과 99%이상의 테스트 정밀도와 0.66이하의 동시 검사속도 특성을 나타내었다.

• 반도체디스플레이기술학회지
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• 제8권4호
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• pp.49-52
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• 2009

We have investigated the effect of the surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of ITO thin films, we have processed photolithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the ITO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the ITO thin films. Device structure was ITO/$\alpha$-NPD/DPVB/Alq3/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer (minolta CS-1000A). The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• 동력기계공학회지
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• 제4권1호
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• pp.45-50
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• 2000

Circuit breakers have traditionally employed mechanical methods to interrupt excessive currents. According to power semiconductor technology advances in power electronic device, some mechanical breakers are replaced with solid state equivalents. Advantages of the contactors using semiconductor devices include faster fault interrupting, fault current limiting, no arc to contain or extinguish and intelligent power control, and high reliability. This paper describes the design of a static $100{\pm}10%V$ and 0 to 50A DC self-protected contactor with 85A "magnetic tripping" and 100A interruption current at $2.2A/{\mu}s$ short circuit of load condition using a new power device the HARRIS MCT (600V-75A). The self-protection circuit of this system is designed by the classical ZnO varistor for energy absorption and turn-off snubber circuit ("C" or "RCD") of the MCT.

• 반도체디스플레이기술학회지
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• 제9권4호
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• pp.25-29
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• 2010

We have investigated the effect of surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of AZO thin films, we have processed photo-lithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the AZO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the AZO thin films. Device structure was AZO/${\alpha}$-NPD/DPVB/$Alq_3$/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer. The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• 전력전자학회논문지
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• 제9권3호
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• pp.203-212
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• 2004

히트파이프를 이용하는 전력반도체 냉각용 히트파이프가 장기간 사용에도 안정된 작동을 이루도록 하기 위해서는 제조 과정에서 발생할 수 있는 산화막 존재 등 문제 요인의 제거와 함께 시험을 통한 확인이 필요하다. 본 연구에서는 전력반도체 냉각용 히트파이프가 요구하는 여러 기하학적, 열적조건에 의해 결정되는 열수송 한계 및 특성과 안정된 작동을 확인하기 위한 시험방법을 제시하고 시험을 통하여 확인된 결과를 정리하였다.

• ETRI Journal
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• 제30권6호
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• pp.833-843
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• 2008

The effect of forward and reverse electrostatic discharge (ESD) on the electro-optical characteristics of oxide vertical-cavity surface-emitting lasers is investigated using a human body model for the purpose of understanding degradation behavior. Forward ESD-induced degradation is complicated, showing three degradation phases depending on ESD voltage, while reverse ESD-induced degradation is relatively simple, exhibiting two phases of degradation divided by a sudden distinctive change in electro-optical characteristics. We demonstrate that the increase in the threshold current is mainly due to the increase in leakage current, nonradiative recombination current, and optical loss. The decrease in the slope efficiency is mainly due to the increase in optical loss.