• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1175-1182
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• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.745-753
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• 2007

Web service, the next generation of distributed computing, is a distributed solution that handles all businesses through standard techniques in the internet. Web service performs its function using web interface. The goal of this thesis is to reduce network overloading. to manage WSDL efficiently, and to provide convenience to service users by simplifying the web service procedure. Web service system proposed in this thesis is based on WSDL Repository that can include UDDI and store WSDL. WSDL Repository manages WSDL by file system and has UDDI Registry embedded within it. Because this system is based on WSDL Repository, Web service supplier must register WSDL when he registers services. Then, users can receive WSDL too when he searches for services.

• Journal of The Korean Association of Information Education
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• v.7 no.1
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• pp.37-47
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• 2003

A grading system of practical word processor skills is designed and implemented by using HWPML(Hangul Word Processor Markup Language) which is a product of Hangul and Computer Co Ltd. By using HWPML, which is a markup tag structure of Hangul file, Hangul files can be edited in other application programs. Authorized users can make questions. However, only the manager is allowed to register answers to the questions in order to maintain the correctness of grading. The result of test is stored in the database and the statistics on pass or failure can be shown interactively. The number of taking test and scores for each user are stored in the database and they can be accessed to whenever the user wants them. Comments on the test results are provided by the manager so that learners can intensity their weak points.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.