• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.1-11
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• 2006

In this paper, we propose a new register file architecture called the Register File Extension for Multi-words or Long-word Operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-words or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. Thus, a single instruction can specify a SIMD-style multi-word operation or a long-word operation. RFEMLO can be applied to general purpose processors by adding instruction set for multi-words or long-word operands and functional units for additional instruction set. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various symmetric and asymmetric cryptographic algorithms. By applying RFEMLO, we could get maximum 62% and 70% reductions in the total instruction count of symmetric and asymmetric cryptographic algorithms respectively. Also, performance results show that a speedup of 1.4 to 2.6 can be obtained in symmetric cryptographic algorithms and a speedup of 2.5 to 3.3 can be obtained for asymmetric cryptographic algorithms when we apply RFEMLO to a processor with an in-order pipeline. We also found that RFEMLO can effectively improve the performance of these cryptographic algorithms with much less cost compared to issue-width increase available in Superscalar implementations. Moreover, the RFEMLO can also be applied to Superscalar processor, leading to additional 83% and 138% performance gain in symmetric and asymmetric cryptographic algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.100-102
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• 1991

In this paper, we use LFSR(Linear Feedback Shift Register) as a kind of pseudo-random one-time pad. Key generator is constructed using r separate LFSR's with IP(Irreducible Polynominal) which are relatively prime. Key generated in this method has high linear complexity. And also, file cryptosystem for file encryption and decryption is constructed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Journal of the Korea Fashion and Costume Design Association
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• v.26 no.1
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• pp.33-44
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• 2024

This study developed e-book content in order to use e-books as a tool to provide more efficient classes to learners who are familiar with smart devices and online spaces. E-book contents were produced using Sigil-0.9.10. The development process is as follows. Before e-book development, it is necessary to prepare manuscript files, image files to be inserted, fonts to be used, and e-book covers. After inserting the book cover images, it is necessary to register the table of contents using the title tag and register the free fonts. Also, a style must be created for text or images used in the main text connected to a file containing the entire text. Then, after separating the entire text file into separate files according to each chapter, the text is completed in turn. E-books were produced focusing on hyperlink functions so that educational content and various example images could be accessed. Currently, there is a lack of research on e-books as textbooks in universities within the fashion design major. In the future, if e-book contents are developed according to the characteristics of courses and the level of learners, they can be used as effective teaching tools.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.65-72
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• 2007

This paper aims to provide information to generate a statistical load model of an educational server by analyzing workload of an e-Learning sewer at Dankook University. The result of the analysis shows file size distribution, access frequency and transmission volume for each file type, access interval, changes in preference and clients access rate by networks. In particular, it had different results from previous studies about video file's size distribution and file distribution based on access frequency. This is because the characteristics of e-learning are influenced by using authoring tools for making into video file and by freeing the number of students who register for a course. The result in this paper can be used as a basic data for studies designed to improve e-learning system architecture and server performance.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.451-454
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• 2004

The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1015-1024
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• 2011

Mobile P2P protocols in ad-hoc networks have gained large attention recently. Although there has been much research on P2P algorithms for wired networks, existing P2P protocols are not suitable for mobile ad-hoc networks because they do not consider mobility of peers. This study proposes a new cluster-based P2P protocol for ad hoc networks which utilizes peer mobility. In typical cluster-based P2P algorithms, each cluster has a super peer and other peers of the cluster register their file list to the super peer. High mobility peers would cause a lot of file list registration traffic because they hand-off between clusters frequently. In the proposed scheme, while peers with low mobility behave in the same way as the peers of the typical cluster-based P2P schemes, peers with high mobility behave differently. They inform their entrance to the cluster region to the super peer but they do not register their file list to the super peer. When a peer wishes to find a file, it first searches the registered file list of the super peer and if fails, query message is broadcasted. We perform mathematical modeling, analysis and optimization of the proposed scheme regarding P2P traffic and associated routing traffic. Numerical results show that the proposed scheme performs much better than or similar to the typical cluster-based P2P scheme and flooding based Gnutella.

• Proceedings of the Acoustical Society of Korea Conference
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• 1995.06a
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• pp.137-140
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• 1995

In the paper, CDMA's vocoder algorithm, QCELP, was analyzed. And, 16-bit programmable DSP core for QCELP was designed. When it is used two MACs in DSP, we can implement low-power DSP and estimate decrease of parameter computation speed. Also, we implemented in FIFO memory using register file to increase the access time of the data. This DSP was designed using logic synthesis tool, COMPASS, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.