• Title/Summary/Keyword: redundant processing

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A CPU-GPU Hybrid System of Environment Perception and 3D Terrain Reconstruction for Unmanned Ground Vehicle

  • Song, Wei;Zou, Shuanghui;Tian, Yifei;Sun, Su;Fong, Simon;Cho, Kyungeun;Qiu, Lvyang
    • Journal of Information Processing Systems
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    • v.14 no.6
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    • pp.1445-1456
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    • 2018
  • Environment perception and three-dimensional (3D) reconstruction tasks are used to provide unmanned ground vehicle (UGV) with driving awareness interfaces. The speed of obstacle segmentation and surrounding terrain reconstruction crucially influences decision making in UGVs. To increase the processing speed of environment information analysis, we develop a CPU-GPU hybrid system of automatic environment perception and 3D terrain reconstruction based on the integration of multiple sensors. The system consists of three functional modules, namely, multi-sensor data collection and pre-processing, environment perception, and 3D reconstruction. To integrate individual datasets collected from different sensors, the pre-processing function registers the sensed LiDAR (light detection and ranging) point clouds, video sequences, and motion information into a global terrain model after filtering redundant and noise data according to the redundancy removal principle. In the environment perception module, the registered discrete points are clustered into ground surface and individual objects by using a ground segmentation method and a connected component labeling algorithm. The estimated ground surface and non-ground objects indicate the terrain to be traversed and obstacles in the environment, thus creating driving awareness. The 3D reconstruction module calibrates the projection matrix between the mounted LiDAR and cameras to map the local point clouds onto the captured video images. Texture meshes and color particle models are used to reconstruct the ground surface and objects of the 3D terrain model, respectively. To accelerate the proposed system, we apply the GPU parallel computation method to implement the applied computer graphics and image processing algorithms in parallel.

A Batch Processing Algorithm for Moving k-Nearest Neighbor Queries in Dynamic Spatial Networks

  • Cho, Hyung-Ju
    • Journal of the Korea Society of Computer and Information
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    • v.26 no.4
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    • pp.63-74
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    • 2021
  • Location-based services (LBSs) are expected to process a large number of spatial queries, such as shortest path and k-nearest neighbor queries that arrive simultaneously at peak periods. Deploying more LBS servers to process these simultaneous spatial queries is a potential solution. However, this significantly increases service operating costs. Recently, batch processing solutions have been proposed to process a set of queries using shareable computation. In this study, we investigate the problem of batch processing moving k-nearest neighbor (MkNN) queries in dynamic spatial networks, where the travel time of each road segment changes frequently based on the traffic conditions. LBS servers based on one-query-at-a-time processing often fail to process simultaneous MkNN queries because of the significant number of redundant computations. We aim to improve the efficiency algorithmically by processing MkNN queries in batches and reusing sharable computations. Extensive evaluation using real-world roadmaps shows the superiority of our solution compared with state-of-the-art methods.

XQuery Query Rewriting for Query Optimization in Distributed Environments (분산 환경에 질의 최적화를 위한 XQuery 질의 재작성)

  • Park, Jong-Hyun;Kang, Ji-Hoon
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.3
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    • pp.1-11
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    • 2009
  • XQuery query proposed by W3C is one of the standard query languages for XML data and is widely accepted by many applications. Therefore the studies for efficient Processing of XQuery query have become a topic of critical importance recently and the optimization of XQuery query is one of new issues in these studies. However, previous researches just focus on the optimization techniques for a specific XML data management system and these optimization techniques can not be used under the any XML data management systems. Also, some previous researches use predefined XML data structure information such as XML schema or DTD for the optimization. In the real situation, however applications do not all refer to the structure information for XML data. Therefore, this paper analyzes only a XQuery query and optimize by using itself of the XQuery query. In this paper, we propose 3 kinds of optimization method that considers the characteristic of XQuery query. First method removes the redundant expressions described in XQuery query second method replaces the processing order of operation and clause in XQuery query and third method rewrites the XQuery query based on FOR clause. In case of third method, we consider FOR clause because generally FOR clause generates a loop in XQuery query and the loop often rises to execution frequency of redundant operation. Through a performance evaluation, we show that the processing time for rewritten queries is less than for original queries. also each method in our XQuery query optimizer can be used separately because the each method is independent.

Variable Length Optimum Convergence Factor Algorithm for Adaptive Filters (적응 필터를 위한 가변 길이 최적 수렴 인자 알고리듬)

  • Boo, In-Hyoung;Kang, Chul-Ho
    • The Journal of the Acoustical Society of Korea
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    • v.13 no.4
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    • pp.77-85
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    • 1994
  • In this study an adaptive algorithm with optimum convergence factor for steepest descent method is proposed, which controls automatically the filter order to take the appropriate level. So far, fixed order filters have been used when adaptive filter is employed according to the priori knowledge or experience in various adaptive signal processing applications. But, it is so difficult to know the filter order needed in real implementations that high order filters have to be performed. As a result, redundant calculations are increased in the case of high order filters. The proposed variable length optimum convergence factor (VLOCF) algorithm takes the appropriated filter order within the given one so that the redundant calculation is decreased to get the enhancement of convergence speed and smaller convergence error during the steady state. The proposed algorithm is evaluated to prove the validity by computer simulation for system Identification.

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Design and Fault Tolerant Routing Scheme of Dual Network in Parallel Processing System (병렬처리 시스템에서의 Dual 네트워크의 설계 및 오류허용 라우팅 전략)

  • 최창훈;김성천
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1169-1181
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    • 1994
  • The Gamma Network contains the redundant path thereby is provides the ability to tolerate the faults occured. However, in case of identical the source and destination number, only a single path exists, therefore there is no way of connecting for the fault situation. In addition, for the dynamic packet routing strategy, it shoed perform backtracking analysis to find the redundant path. In this paper we proposed a new network, Dual Network, to resolve these drawbacks. The Dual Network uses switching elements about the same network size as the Gamma Network except first and last stage, and it is more efficient than the Gamma Network, for it has reduced the switching stage by one. And since is used a destination tag routing scheme for the control algorithm, it has on advantage of becoming of simpler and faster routing control.

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An Adaptive FEC based Error Control Algorithm for VoIP (VoIP를 위한 적응적 FEC 기반 에러 제어 알고리즘)

  • Choe, Tae-Uk;Jeong, Gi-Dong
    • The KIPS Transactions:PartC
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    • v.9C no.3
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    • pp.375-384
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    • 2002
  • In the current Internet, the QoS of interactive applications is hardly guaranteed because of variable bandwidth, packet loss and delay. Moreover, VoIP which is becoming an important part of the information infra-structure in these days, is susceptible to network packet loss and end-to-end delay. Therefore, it needs error control mechanisms in network level or application level. The FEC-based error control mechanisms are used for interactive audio application such as VoIP. The FEC sends a main information along with redundant information to recover the lost packets and adjusts redundant information depending on network conditions to reduce the bandwidth overhead. However, because most of the error control mechanisms do not consider end-to-end delay but packet loss rate, their performances are poor. In this paper, we propose a new error control algorithm, SCCRP, considering packet loss rate as well as end-to-end delay. Through experiments, we confirm that the SCCRP has a lower packet loss rate and a lower end-to-end delay after reconstruction.

A New Complex-Number Multiplication Algorithm using Radix-4 Booth Recoding and RB Arithmetic, and a 10-bit CMAC Core Design (Radix-4 Booth Recoding과 RB 연산을 이용한 새로운 복소수 승산 알고리듬 및 10-bit CMAC코어 설계)

  • 김호하;신경욱
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.9
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    • pp.11-20
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    • 1998
  • High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

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A Fast Parity Resynchronization Scheme for Small and Mid-sized RAIDs (중소형 레이드를 위한 빠른 패리티 재동기화 기법)

  • Baek, Sung Hoon;Park, Ki-Wong
    • KIPS Transactions on Computer and Communication Systems
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    • v.2 no.10
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    • pp.413-420
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    • 2013
  • Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

Synchronization Method Design of Redundant Flight Control Computer for UAV (무인기를 위한 이중화 비행제어컴퓨터의 동기화 설계)

  • Lee, Young Seo;Kang, Shin Woo;Lee, Hee Gon;Ahn, Tae-Sik
    • Journal of Advanced Navigation Technology
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    • v.25 no.4
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    • pp.273-279
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    • 2021
  • A flight control computer(FLCC) applied to an unmanned aerial vehicle(UAV) is a safety-critical item, and which is designed in a multiple structure to increase the reliability of operation by securing fault tolerance. These FLCC of multiple structure should be designed so that each independent processing/control components can perform the same operation at the same time. And for this reason, a synchronization algorithm for synchronizing the operation between FLCCs should be included in an operational flight program. In this paper, we propose a software design method for synchronization between dual FLCCs applied to UAVs. The proposed synchronization method is designed to synchronize using only the minimum hardware resources to reduce a failure rate. In addition, the proposed synchronization method is designed to minimized synchronization errors due to a timer operation by designing in consideration of operation characteristics of the hardware timer used for the synchronization.

Frequency-Code Domain Contention in Multi-antenna Multicarrier Wireless Networks

  • Lv, Shaohe;Zhang, Yiwei;Li, Wen;Lu, Yong;Dong, Xuan;Wang, Xiaodong;Zhou, Xingming
    • Journal of Communications and Networks
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    • v.18 no.2
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    • pp.218-226
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    • 2016
  • Coordination among users is an inevitable but time-consuming operation in wireless networks. It severely limit the system performance when the data rate is high. We present FC-MAC, a novel MAC protocol that can complete a contention within one contention slot over a joint frequency-code domain. When a node takes part in the contention, it generates randomly a contention vector (CV), which is a binary sequence of length equal to the number of available orthogonal frequency division multiplexing (OFDM) subcarriers. In FC-MAC, different user is assigned with a distinct signature (i.e., PN sequence). A node sends the signature at specific subcarriers and uses the sequence of the ON/OFF states of all subcarriers to indicate the chosen CV. Meanwhile, every node uses the redundant antennas to detect the CVs of other nodes. The node with the minimum CV becomes the winner. The experimental results show that, the collision probability of FC-MAC is as low as 0.05% when the network has 100 nodes. In comparison with IEEE 802.11, contention time is reduced by 50-80% and the throughput gain is up to 200%.