• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.681-691
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• 1986

To represent the relations of the data dependency and resource conflict among micro-operations(MOP's) in the compaction process of microprograms, we propose a DDM (data dependent matrix) representation method instead of the DAG (conventional directed acyclic graph). Also, we propose a global compaction algorithm of microprograms to prevent a kind of block copying by cutting the trace at a junction block. The DDM method and compaction algoristhm have been applied to the Lah's example. The results shows that the proposed algorithm is more efficient than the conventional algorithms in reducing in reducing the total execution time and control memory space.

• Korean Management Science Review
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• v.12 no.2
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• pp.31-42
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• 1995

The ordering method is used to reduce the fill-ins in interior point methods. In ordering, the data structure plays an important role. In this paper, first, we compare the efficiency and the memory storage requirement of the quotient graph structure and the clique storage. Next, we propose a method of reducing the number of cliques and a data structure for clique storage. Finally, we apply a method of merging rows and absorbing cliques and show the experimental results.

• Journal of IKEEE
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• v.12 no.2
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• pp.75-80
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• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.219-222
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• 2003

The Capacitor DAC with gamma correction is proposed for TFT-LCD (Liquid Crystal Display) driver application. It is based on two ideas. First, 6bit digital code is converted 8bit digital code by memory circuit (Look Up Table) for gamma correction. second, weighted voltage ratio DAC is proposed for reducing area and power consumption.

• 전기의세계
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• v.29 no.10
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• pp.660-666
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• 1980

The finite leement method is a effetive analysis technique for obtaining approximate solutions of continuum problems with boundary conditions. This paper deals with the programming for the application of this method and the preciser analysis of the magnetic field in the air gap of the linear stepper motor by the method. The finite element analysis based on the variational principle is adopted and the computer program for reducing input data and a large number of the memory words required by the system matrix is presented. The 2-dimensional analysis of the air gap is made and several cases according to varying the position are considered.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.262-263
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• 2018

최근 디스플레이 크기 및 영상 해상도가 커짐에 따라 디스플레이와 외부 메모리 간 대역폭이 큰 부담이 되고 있다. 본 논문은 이런 문제를 해결하기 위해 라인 단위 영상 압축 기법을 제안한다. 방향성 인트라 예측, 컬러 성분 간 보상 등으로 구성된 제안기법은 50dB 정도 PSNR 에서 최대 12:1 정도의 압축률을 보인다.

• Journal of the Korean Physical Society
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• v.73 no.12
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• pp.1808-1813
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• 2018

I develop a transfer matrix algorithm for computing the geometric quantities of a square lattice polymer with nearest-neighbor interactions. The radius of gyration, the end-to-end distance, and the monomer-to-end distance were computed as functions of the temperature. The computation time scales as ${\lesssim}1.8^N$ with a chain length N, in contrast to the explicit enumeration where the scaling is ${\sim}2.7^N$. Various techniques for reducing memory requirements are implemented.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.1035-1038
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• 2008

가상 메모리의 스왑 저장 장치로서 플래시 메모리를 사용하는 경우, 시스템을 기동할 때 스왑 영역의 초기화를 위한 삭제 연산이 요구되어 기동 시간이 오래 걸리는 문제점이 있다. 본 논문에서는 스왑 영역의 플래시 메모리 내용을 모두 삭제하지 않고 일부만을 삭제함으로서 기동 시간을 줄일 수 있는 방법을 연구하였다.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.571-582
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• 2005

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that dose not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read and write operations is a page. A NAND flash file system called YAFFS has been proposed. But YAFFS has several problems to be addressed. In this paper, the Reliable Flash File System(RFFS) for NAND flash memory is designed and evaluated. In designing a file system the following four issues must be considered in particular for the design: (i) to minimize a repairing time when the system fault occurs, (ii) to balance the number of block erase operations by offering wear leveling policy, and (iii) to reduce turnaround time of memory operations by reducing the amount of data written. We demonstrate and evaluate the performance of the proposed schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).