• Nuclear Medicine and Molecular Imaging
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• v.43 no.5
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• pp.443-450
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• 2009

Purpose: Conventional image reconstruction uses simplified physical models of projection. However, real physics, for example 3D reconstruction, takes too long time to process all the data in clinic and is unable in a common reconstruction machine because of the large memory for complex physical models. We suggest the realistic distributed memory model of fast-reconstruction using parallel processing on personal computers to enable large-scale technologies. Materials and Methods: The preliminary tests for the possibility on virtual manchines and various performance test on commercial super computer, Tachyon were performed. Expectation maximization algorithm with common 2D projection and realistic 3D line of response were tested. Since the process time was getting slower (max 6 times) after a certain iteration, optimization for compiler was performed to maximize the efficiency of parallelization. Results: Parallel processing of a program on multiple computers was available on Linux with MPICH and NFS. We verified that differences between parallel processed image and single processed image at the same iterations were under the significant digits of floating point number, about 6 bit. Double processors showed good efficiency (1.96 times) of parallel computing. Delay phenomenon was solved by vectorization method using SSE. Conclusion: Through the study, realistic parallel computing system in clinic was established to be able to reconstruct by plenty of memory using the realistic physical models which was impossible to simplify.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.11a
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• pp.669-672
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• 2006

본 연구팀은 유비쿼터스 게임 플랫폼을 위한 Embedded C++ 컴파일러를 개발하였으며, 컴파일러 개발 과정에서 객체지향언어인 C++과 Java 언어를 모두 수용할 수 있는 심벌 테이블을 설계하였다. 심벌 테이블은 컴파일러의 어휘 분석과 구문 분석 과정을 거친 후 SDT(syntax-directed translation)에 의해 생성된 AST(Abstract Syntax Tree)를 분석하여 인식된 명칭(identifier)과 그 속성(attribute)들을 수집하여 저장하는 자료구조로써, 심벌 테이블에 저장된 속성들은 의미 분석(semantic analysis) 단계에서 수집된 속성과 참조된 명칭의 사용이 타당한지를 검사하고, 코드 생성(code generation) 단계에서 올바른 코드가 생성되도록 하는 중요한 요소이다. 따라서 심벌 테이블의 설계가 올바른지와 입력된 속성이 정확한지에 대한 검증과 분석은 필수 불가결하다. 본 논문에서는 컴파일러 개발과정에서 설계한 심벌 테이블을 검증하고 분석하기 위한 목적으로써 심벌 테이블을 이용하여 선언문을 복원시키는 역번역기(detranslator)에 대하여 기술한다. 구현된 역번역기는 C++ 컴파일러와 Java 컴파일러의 선언문 처리 과정에서 심벌 테이블에 입력된 속성들을 본래의 입력 프로그램으로 역번역한다. 따라서 역번역기를 통하여 심벌 테이블의 완전성과 심벌 테이블에 입력된 속성 정보의 정확성을 쉽게 검증할 수 있으며, 역번역과 함께 출력되는 디버그 정보를 이용하여 효율적으로 컴파일러의 개발과 수정을 할 수 있다.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.37-44
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• 2002

Most researches of transforming sequential programs into parallel programs have been based on the loop structure transformation method. However, most programs have implicit interprocedure parallelism. This paper suggests a way of extracting parallelism from the loops with procedure calls using the data dependency elimination method. Most parallelization of the loop with procedure calls have been conducted for extracting parallelism from the uniform code. In this paper, we propose interprocedural transformation, which can be apply to both uniform and nonuniform code. We show the examples of uniform, nonuniform, and complex code parallelization. We then evaluated the performance of the various transformation methods using the CRAY-T3E system. The comparison results show that the proposed algorithm out-performs other conventional methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.