• Journal of Positioning, Navigation, and Timing
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• v.8 no.4
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• pp.209-214
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• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.478-480
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• 2005

The AIS(Automatic Identification System) transmits the position of ships and other information to prevent accidents which could occur in the sea. It has to be developed SOTDMA(Self-Organized Time Division Multiple Access) Algorithm which is important on wireless communication method for the AIS because It is based on ITU(International Telecommunication Union) M.1371-1 of the international standard therefore, we need to develop a performance evaluation simulator efficiently to develop and analyze SOTDMA Algorithm. This paper shows the method of designing it. Real ships access The VHF maritime mobile band but in this performance evaluation simulator several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. The ships apply for real virtual data which got from assistance hardware and The SOTDMA Algorithm driving state verifies the performance evaluation simulator by IEC(International Electrotechnical commission) 61993-2. After verifying results the performance evaluation simulator is correctly satisfied with IEC 61993-2. So we expect that it helps not only the AIS technology developed but also verify new SOTDMA Algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.44-57
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• 2016

Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

• Proceedings of the IEEK Conference
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• summer
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• pp.391-394
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5kbytes for program code. Maximum required time of 29.2ms for processing a frame of 32ms of speech validates real-time operation of the implemented system.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.285-285
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• 2016

Resistive random access memory devices have been widely studied due to their high performance characteristics, such as high scalability, fast switching, and low power consumption. However, fluctuation in operational parameters remains a critical weakness that leads to device failures. Although the random formation and rupture of conducting filaments (CFs) in an oxide matrix during resistive switching processes have been proposed as the origin of such fluctuations, direct observations of the formation and rupture of CFs at the device scale during resistive switching processes have been limited by the lack of real-time large-area imaging methods. Here, a novel imaging method is proposed for monitoring CF formation and rupture across the whole area of a memory cell during resistive switching. A hybrid structure consisting of a resistive random access memory and a light-emitting diode enables real-time monitoring of CF configuration during various resistive switching processes including forming, semi-forming, stable/unstable set/reset switching, and repetitive set switching over 50 cycles.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.587-592
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• 2004

Context-aware computing systems require real-time context reasoning process for context awareness. Context reasoning can be done by comparing input information from sensors with knowledge-base within system. This method is identical with it of rule-based systems. In this paper, we propose hardware rule-based system architecture which can process context reasoning in real-time. Compared to previous architecture, hardware rule-based system architecture can reduce the number of constraints on rule representations and combinations of condition terms in rules. The modified content addressable memory, crossbar switch network and pre-processing module are used for reducing constraints. Using SystemC for description can provide easy modification of system configuration later.

• Smart Structures and Systems
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• v.13 no.2
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• pp.203-217
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• 2014

Due to the shift in paradigm from passive control to adaptive control, smart tuned mass dampers (STMDs) have received considerable attention for vibration control in tall buildings and bridges. STMDs are superior to tuned mass dampers (TMDs) in reducing the response of the primary structure. Unlike TMDs, STMDs are capable of accommodating the changes in primary structure properties, due to damage or deterioration, by tuning in real time based on a local feedback. In this paper, a novel adaptive-length pendulum (ALP) damper is developed and experimentally verified. Length of the pendulum is adjusted in real time using a shape memory alloy (SMA) wire actuator. This can be achieved in two ways i) by changing the amount of current in the SMA wire actuator or ii) by changing the effective length of current carrying SMA wire. Using an instantaneous frequency tracking algorithm, the dominant frequency of the structure can be tracked from a local feedback signal, then the length of pendulum is adjusted to match the dominant frequency. Effectiveness of the proposed ALP-STMD mechanism, combined with the STFT frequency tracking control algorithm, is verified experimentally on a prototype two-storey shear frame. It has been observed through experimental studies that the ALP-STMD absorbs most of the input energy associated in the vicinity of tuned frequency of the pendulum damper. The reduction of storey displacements up to 80 % when subjected to forced excitation (harmonic and chirp-signal) and a faster decay rate during free vibration is observed in the experiments.

• The Journal of the Korea Contents Association
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• v.22 no.6
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• pp.56-68
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• 2022

Recently, as the demand for real-time processing increases, studies on a dynamic graph that changes over time has been actively done. There is a connected components processing algorithm as one of the algorithms for analyzing dynamic graphs. GPUs are suitable for large-scale graph calculations due to their high memory bandwidth and computational performance. However, when computing the connected components of a dynamic graph using the GPU, frequent data exchange occurs between the CPU and the GPU during real graph processing due to the limited memory of the GPU. The proposed scheme utilizes the Weighted-Quick-Union algorithm to process large-scale graphs on the GPU. It supports fast connected components computation by applying the size to the connected component label. It computes the connected component by determining the parts to be recalculated and minimizing the data to be transmitted to the GPU. In addition, we propose a processing structure in which the GPU and the CPU execute asynchronously to reduce the data transfer time between GPU and CPU. We show the excellence of the proposed scheme through performance evaluation using real dataset.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.