• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.419-421
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• 1987

The high-speed tendency of Programmable Controller requires a fast processing of instruction. This project investigate the instruction execution system for a fast processing in Programmable Controller.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.407-412
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• 1987

A large scale programmable controller is developed which adopts a multiprocessor structure. The developed programmable controller consists of the programmer, the system controller, and the input-output unit. The structure and characteristics of the system controller will be described. The PC has a special hardware scheme to solve the Boolean logic instructions of the sequence control programs. The multiprocessor structure and the special hardware enables, the real time operation and the high speed scanning which is prerequisite to the large scale, programmable controller even for many I/O points.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.1
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• pp.1-9
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• 1985

In this study we described Binary-Decision Method Programmable Controller that is faster than conventional Programmable Controller (P.C) using the Boolean method. An algorithm for the optimal BD program was systematically developed by using the incomplete multiple output function and the residual characteristic function. The potential applications of BD programmable controller for the problems of industrial control were illustrated, which include on-off sequential control function and also the tasks involving continuous data processing and PID control. An example was presented that has shown how BD programmable controller and ICU (Industrial Control Unit) controller can be applied to the sequential logics.

• 전기의세계
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• v.36 no.7
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• pp.522-525
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• 1987

본고의 내용은 다음과 같다. 1. Programmable Controller의 역사 및 개요 2. 공장 자동화에서 PLC의 역할 3. PLC의 기술 동향 4. PLC의 시장 동향

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.169-174
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• 1986

This thesis investigates the scanning time ; one of the most important performance index of Programmable Controller(PC). The multiprocessor architecture of the large PC considered in this thesis are classified as architecture 1 and architecture 2 by the bus control methods. The queuing model of each architecture is developed. Form the analysis it is observed that in the case of the number of processors less than 3 the best architecture of the large PC is the architecture 2 and in the case of the number of processors greater than 2 the best architecture of the large PC is the architecture 1.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.29-38
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• 1997

As the trend of the automation is increasing, the usage of the programmable automation equipments like programmable controller(PC), numerical controller(NC), distributed control systems(DCS) and robot controller is greatly expanding in the area of the industrial equipments. But the development of the programing language for the programmable automatic equipment is rarely accomplished. In this paper, we propose design and implementation technique of the real-time mechanism control language by adding time constraint constructs and timing analysis constructs ot conditional statement and iteration statement of a programming language. Moreover, we made it possible to predict plausibility of time constraint constructs of a real time application program at compilation time and developing execution time analysiss technique.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.33-38
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• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.637-646
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• 1986

In this paper, we investigate and characterize the parallel processing of a hybrid system interfacing binary decision(BD) programmable controller with a microcomputer. The generation of analog signals and estimation of data, which can not properly be performed by the BD programmable controller alone, have been done by the the expanded controller utilizing BD/Micdro P.C. In addition, implementation of its hardware and software is considered.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.7
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• pp.254-260
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• 1983

In this paper a basic design procedure for programmable instruments of IEEE-488 BUS system has been discussed by designing a specific programmable frequency counter with its hardware and software. The designed programmable frequency counter has a programmable range switch and a function of the programable number of measurements. It contains five basic functions(Talker. Listener, Source handshake, Accepter handshake and Controller) of a IEEE-488 BUS and the Device-Trigger as a supplimentary function. The hardware has been built along with 6800 MPU and 68488 GPIA, and its software has included initialization, interrupt handler, BI.GET,BO and controller routines, The designed system given in this paper has been successfuly tested via some experiments.