• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• 대한조선학회논문집
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• 제52권5호
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• pp.365-371
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• 2015

Hull plate consists of various types of curved plates and there also exists corresponding processing methods. Typically, curved plates can be divided into convex type and saddle type. Large amount of research has been conducted mainly focusing on application of processing method of convex type, saddle type and hybrid type, but research on determination and processing method application of the most difficult S-shaped curved plate that has inflection lines has not been carried out yet. In this paper, as the fundamental research of appropriate processing method application, a calculation method is proposed to calculate inflection lines on curved plates. In order to calculate inflection lines, normal curvature and information of fabricated curved plates should be utilized. We compare the workability of the fabrication for hull plate using inflection line.

• 한국자동차공학회논문집
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• 제18권4호
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• pp.54-61
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• 2010

In this paper, we design the signal processing unit to effectively support the proposed algorithm for an automotive Frequency Modulation Continuous Wave(FMCW) radar. In the proposed method, we can obtain the distance and velocity with improved error depending on each range(long, middle, and short) of the target. Since a high computational capacity is required to obtain more accurate distance and velocity for target in near range, the proposed signal processing unit employs the time de-interleaving and the frequency interpolation method to overcome the limitation. Moreover, for real-time signal processing, the parallel architecture is used to extract simultaneously the distance and velocity in each range.

• 전자공학회논문지A
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• 제30A권3호
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권4호
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• pp.1146-1165
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• 2022

A huge amount of data in the form of videos and images is being produced owning to advancements in sensor technology. Use of low performance commodity hardware coupled with resource heavy image processing and analyzing approaches to infer and extract actionable insights from this data poses a bottleneck for timely decision making. Current approach of GPU assisted and cloud-based architecture video analysis techniques give significant performance gain, but its usage is constrained by financial considerations and extremely complex architecture level details. In this paper we propose a data pipeline system that uses open-source tools such as Apache Spark, Kafka and OpenCV running over commodity hardware for video stream processing and image processing in a distributed environment. Experimental results show that our proposed approach eliminates the need of GPU based hardware and cloud computing infrastructure to achieve efficient video steam processing for face detection with increased throughput, scalability and better performance.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• 전자공학회논문지C
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• 제34C권9호
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• pp.10-21
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• 1997

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1791-1796
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• 2004

Recently, great improvements have been made in developing autonomous underwater vehicles (AUVs) using stateof- the-art technologies for various kinds of sophisticated underwater missions. To meet increasing demands posed on AUVs, a powerful on-board computer system and an accurate sensor system with an well-organized control system architecture are needed. In this paper, a new control system architecture is proposed for AUV, ORCA (Oceanic Reinforced Cruising Agent) which is being currently developed by Korea Research Institute of Ships and Ocean Engineering (KRISO). The proposed architecture uses a hybrid architecture that combines a hierarchical architecture and a behavior based control architecture with an evaluator for coordinating between the architectures. This paper also proposed a sensor fusion structure based on the definition of 4 categories of sensors called grouping and 5-step data processing procedure. The development of the AUV, ORCA involving the system architecture, vehicle layout, and hardware configuration of on-board system are described.

• 디지털콘텐츠학회 논문지
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• 제8권4호
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• pp.615-622
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• 2007

유저에게 다양한 게임 플레이 경험을 제공하기 위해 게임 엔진은 다양한 게임 내 개체 간 상호 작용을 다룰 수 있는 엔진 구조를 가져야 한다. 이를 위해 메시지 기반 게임 엔진 구조가 사용 된다. 그러나 메시지 기반 게임 엔진 구조만으로는 게임 세계를 특정한 스토리라인 기반으로 변화시켜 나가기 어렵다. 이는 메시지 기반 시스템과 같은 event-driven system 자체가 하나하나의 메시지 처리에는 적합하지만 이보다 상위의 보다 큰 논리적인 작업 단위를 처리하기에 적합한 구조는 아니기 때문이다. 이를 위해 storyline 개체를 만들 지속적으로 storyline의 스토리 진행 함수를 호출함으로써 메시지 기반 시스템의 자유로움은 유지하면서 게임 세계에 특정 storyline의 진행을 추가할 수 있는 게임 엔진 구조를 제안한다.

• 한국정보처리학회논문지
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• 제6권5호
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.