• Title/Summary/Keyword: platform-based SoC design

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Ubiquitous Healthcare Monitoring System based on Web 2.0 (웹 2.0 기반의 유비쿼터스 헬스케어 모니터링 시스템)

  • Jeong, Pil-Seong;Oh, Young-Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.4C
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    • pp.321-328
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    • 2012
  • The Mobile device like smart phone is a small computing device and easy to carry around. The Mobile devices are wildly being used as desktop personal computer and can served individual services. Because of compatibility of applications working on mobile devices are not good, so developer need to develop it that match changes in platform fetures. In this paper, we design and implementate ubiquitous healthcare monitoring system that can be runs on many different platforms using HTML5 as a standard web development language and jQuery as a javascript library. Ubiquitous healthcare monitoring system is runs on on many different platforms like mobile platforms and desktop web browsers.

I3A Framework of Defense Network Centric Based C2 Facilities (국방 NC 기반 C2 시설 I3A Framework)

  • Kim, Young-Dong;Lee, Tae-Gong;Park, Bum-Shik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.8
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    • pp.615-625
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    • 2014
  • Ministry of National Defense, MND, established a "Master Plan of Military Facility" in 2010 based on the defense reform to prepare for future war. It was a plan for consolidating small military facilities into battalion units, reflecting on and preparing for the needs of various changes in defense environment as well as balanced growth of ROK Army, Navy, and Air Force. However, to move forward with "Military Facility Master Plan," current design criteria for military facilities need to be revised to be enacted due to numerous calculation errors in facility footprints because of the absence of a sound facility criteria. Because the future war environment will be changed from Platform basis to Network Centric Warfare basis, Command & Control capability of C4I systems is getting more important. Therefore, Successful mission accomplishment can be secured by convergence of facility and military Information Technology(IT). So, MND should quickly prepare for the operational guidance, design criteria and policy that are suitable for Network Centric Warfare accomplishment, and implement infrastructure of IT and installation of C2 facility in conjunction with consolidation movement of military facilities. In this paper, we propose the defense I3A framework in order to solve this problem.

Design and Implementation of Double-Key based Light Weight Security Protocol in Ubiquitous Sensor Network (유비쿼터스 센서 네트워크에서 더블키를 이용한 경량 보안 프로토콜 설계 및 구현)

  • Zhung, Yon-Il;Lee, Sung-Young
    • The KIPS Transactions:PartC
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    • v.14C no.3 s.113
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    • pp.239-254
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    • 2007
  • Ubiquitous computing supports environment to freely connect to network without restrictions of place and time. This environment enables easy access and sharing of information, but because of easy unauthorized accesses, specified security policy is needed. Especially, ubiquitous sensor network devices use limited power and are small in size, so, many restrictions on policies are bound to happen. This paper proposes double-key based light weight security protocol, independent to specific sensor OS, platform and routing protocol in ubiquitous sensor network. The proposed protocol supports safe symmetric key distribution, and allows security manager to change and manage security levels and keys. This had a strong merit by which small process can make large security measures. In the performance evaluation, the proposed light weight security protocol using double-key in ubiquitous sensor network allows relatively efficient low power security policy. It will be efficient to ubiquitous sensor network, such as smart of ace and smart home.

Development of Modeling Support System for Lower Arm in Automobile Suspension Module (자동차 서스펜션 로워암의 모델링 보조시스템 개발)

  • Lee T.H.;Shin S.Y.;Suh C.H.;Kwon T.W.;Han S.H.
    • Korean Journal of Computational Design and Engineering
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    • v.11 no.1
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    • pp.49-56
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    • 2006
  • In this study, the modeling support system was developed which can make easy and fast FE-modeling and verify the results of static and durability analysis for the lower arm, one of the important parts in automobile suspension module. It took into account of the whole complicated design processes verifying the durability coefficients evaluated by fatigue analysis, which should be used to satisfy a design criteria. To guide the FE-modeling the drive page was constructed by using HTML and XML, which was based on expert's know-hows. It is able to integrate the processes to design the lower arm in practice, so that the standardization of its FE-Modeling is achieved, consequently. The 3 dimensional CAD's geometrical data were changed automatically into pre-defined shell elements under the concept of mesh-offset technique, and then welding elements were treated to connect between target and basic surfaces constructed by the shell elements. This system has also a user interface to control boundary and load ing conditions applied in performing of the static and durability analysis, in which many load cases can be applied simply with the MPCs driven by just few mouse clicks. These were implemented on the platform of MSC.Patran and utilized ANSYS, MSC.Nastran and MSC.Fatigue as the solver of the analysis performed. The developed system brings not only significant decreasing of man-hours required in FE-modeling process, but also obtaining of satisfied qualities in analyzed results. It will be integrated in a part of virtual prototyping module of the developing e-engineering framework.

Low-power IP Design and FPGA Implementation for H.264/AVC Encoder (H.264/AVC Encoder용 저전력 IP 설계 및 FPGA 구현)

  • Jang, Young-Beom;Choi, Dong-Kyu;Han, Jae-Woong;Kim, Do-Han;Kim, Bee-Chul;Park, Jin-Su;Han, Kyu-Hoon;Hur, Eun-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.5
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    • pp.43-51
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    • 2008
  • In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

An XML Structure Translation System using Schema Structure Data Mapping (스키마 구조 데이타 매핑을 이용한 XML 구조변환 시스템)

  • 송종철;김창수;정회경
    • Journal of KIISE:Computing Practices and Letters
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    • v.10 no.5
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    • pp.406-418
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    • 2004
  • Last days, various kinds of applications and system were individually introduced into specific groups or enterprises by different objective without considering interoperability among those. However, the environment for data processing is changing rapidly in these days. And now the necessity is growing to integrate and couple applications and system in the process dimension for more flexible and quicker data processing on these application programs and system. When integrating these application programs or system, an integration based on XML is recommended as it is one of good methods which will the additional cost and satisfy the requirements of the integration. This is because the XML is not only device-independent data type which can be used any platform, but also it uses XSLT, the document conversion standard established by W3C, which allows easy data conversion from one to another type on occasion of demands. This paper studies a design and implementation of system to convert XML structure. This system shows the structure of source- side providing data and destination-side processing data with using XML schema that defines structural information of a XML document. And this system defines the structure relationship of desired form as mapping structural information and data. This system creates the XSLT document that defines conversion rule between two structures based information which is defined. The XSLT document which is created as described above will convert data to be appropriate to the structure of the destination- side. By implementing this system, it is able to apply a document into various kinds of structure without considering specific system or platform and it is able to construct XSLT document to which meaning of desired form can be given. This paper aims to offer a process conversion between documents and to improve interoperability and scalability, so that we can contribute to build XML document processing environment

FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking (블라인드 워터마킹을 내장한 실시간 비디오 코덱의 FPGA기반 단일 칩 구조 및 설계)

  • 서영호;김대경;유지상;김동욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8C
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    • pp.1113-1124
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    • 2004
  • In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).