• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2013년도 추계학술대회
• /
• pp.719-721
• /
• 2013

지문인식센서로부터 획득한 이미지를 처리하기 위한 알고리즘에서 세선화 단계가 차지하는 비율이 전체 마이크로프로세서 동작 사이클의 39%에 이른다. 세선화 단계는 가보필터와 달리 초월함수 등 복잡한 함수를 사용하는 동작이 아니므로 하드웨어로 구현하는 것이 전체 시스템의 소형화와 저전력에 도움이 된다. 본 논문에서는 반복작인 단순동작을 수행하는 세선화를 위한 $64{\times}64$ 픽셀이미지 처리기를 RTL 수준에서 설계하고 FPGA 환경에서 논리합성을 통하여 그 동작을 검증하고자 한다. 이를 통하여 향후 저성능 마이크로콘트롤러와 세선화 프로세서 내장형 지문인식 SoC 의 가능성을 보여준다.

• 한국진공학회지
• /
• 제10권1호
• /
• pp.72-80
• /
• 2001

본 논문에서는 ELA(excimer laser annealing) 및 SMC(silicide mediated crystallization) 공정으로 제작된 다결정 실리콘 TFT-LCD(Thin Film Transistor-Liquid Crystal Display) 화소의 전기적 특성을 Spice회로 시뮬레이션을 통해 비교 분석하였다. 복잡한 TFT-LCD 어레이 (array) 회로의 전기적 특성 분석을 위하여 GUI(Graphic User Interface) 방식으로 손쉽게 복잡한 회로를 구성할 수 있는 PSpice에 AIM-Spice의 다결정 실리콘 박막 트랜지스터 소자 모델을 이식하고, AIM-Spice의 변수 추출법을 개선 체계화하였으며 ELA 및 SMC공정으로 각기 제작된 다결정 실리콘 박막트랜지스터에 적용하여 단위 화소 및 라인 RC 지연을 고려한 화소 특성을 비교 분석하였다. 비교 결과 ELA 다결정 실리콘 박막 트랜지스터 소자가 SMC에 비해 TFT-LCD의 화소 충전 시간 및 킥백(kickback) 전압 특성이 모두 우수하게 나타남을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.148-149
• /
• 2008

As infrared light is radiated, the CMOS Readout IC (ROIC) for the microbolometer type infrared sensor detects voltage or current when the resistance value in the bolometer sensor varies. One of the serious problems in designing the ROIC is that resistances in the bolometer and reference resistor have process variation. This means that each pixel does not have the same resistance, causing serious fixed pattern noise problems in sensor operations. In this paper, Reference resistor compensation technique was proposed. This technique is to compensate the reference resistance considering the process variation, and it has the same reference resistance value as a bolometer cell resistance by using a comparator and a cross coupled latch.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2018년도 추계학술대회
• /
• pp.180-181
• /
• 2018

JPEG은 가장 널리 사용되는 표준 이미지 압축기술이다. 본 논문에서는 이미지 압축 알고리즘을 소개하고 압축 및 압축 해제의 각 단계를 서술하고자 한다. 이미지 압축은 디지털 이미지를 데이터 압축을 적용하는 과정이다. 이산여현변환은 시간 도메인에서 주파수 도메인으로 변환하는 기술이다. 먼저, 이미지는 8 by 8 픽셀 블록으로 분할하게 된다. 둘째, 위에서 아래로 왼쪽에서 오른쪽으로 진행하면서 DCT가 각각의 블록에 적용하게 된다. 셋째, 각 블록은 양자화를 통해 압축을 진행한다. 넷째, 이미지를 구성하는 압축된 블록의 배열은 크게 줄어든 공간에 저장된다. 끝으로, 원하는 경우 이미지는 역 이산여현변환 (IDCT)을 사용하는 프로세스인 압축 해제를 통해 재구성하게 된다.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권4호
• /
• pp.237-250
• /
• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• 한국통신학회논문지
• /
• 제39A권5호
• /
• pp.215-219
• /
• 2014

In holographic data storage (HDS), a high transmission rate is accomplished through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data. Although HDS has many advantages in terms of storage capacity and data transmission rates, it also features problems, such as 2D intersymbol interference (ISI) by neighboring pixels and interpage interference (IPI) by multiple images stored in the same holographic volume. Modulation codes can be used to remove these problems. We introduce a 2D 8/9 error-correcting modulation code. The proposed modulation code exploits the trellis-coded modulation scheme, and the code rate is larger (about 0.889) than that of the conventional 6/8 balanced modulation code (an increase of approximately 13.9%). The performance of the bit error rate (BER) with the proposed scheme was improved compared with that of the 6/8 balanced modulation code and the simple 8/9 code without the trellis scheme.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
• /
• pp.388-391
• /
• 2003

The properties of these detectors can be controlled by electronics and exposure conditions. Flat-panel detectors for digital diagnostic imaging convert incident x-ray images to charge images. Flat panel detectors gain more interest real time medical x-ray imaging. Active area of flat panel detector is $14{\times}17$ inch. Detector is based on a $2560{\times}3072$ away of photoconductor and TFT pixels. X-ray conversion layer is deposited upper TFT array flat panel with a 500m by thermal deposition technology. Thickness uniformity of this layer is made of thickness control technology(5%) of thermal deposition system. Each $139m{\times}139m$ pixel is made of thin film transistor technology, a storage capacitor and charge collection electrode having geometrical fill factor of 86%. Using the separate driving system of two dimensional mosaic modules for large area, that is able to 4.2 second per frame. Imaging performance is suited for digital radiography imaging substitute by conventional radiography film system..

• 한국컴퓨터정보학회논문지
• /
• 제23권1호
• /
• pp.33-39
• /
• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Nuclear Engineering and Technology
• /
• 제53권1호
• /
• pp.199-207
• /
• 2021

This paper deals with accurate image reconstruction of gamma camera using a coded-aperture mask based on pixel-type CsI(Tl) scintillator coupled with silicon photomultipliers (SiPMs) array. Coded-aperture imaging (CAI) system typically has a smaller effective viewing angle than Compton camera. Thus, if the position of the gamma source to be searched is out of the fully-coded field-of-view (FCFOV) region of the CAI system, artifacts can be generated when the image is reconstructed by using the conventional cross-correlation (CC) method. In this work, we propose an effective method for more accurate reconstruction in CAI considering the source distribution of partially-coded field-of-view (PCFOV) in the reconstruction in attempt to overcome this drawback. We employed an iterative algorithm based on compressed-sensing (CS) and compared the reconstruction quality with that of the CC algorithm. Both algorithms were implemented and performed a systematic Monte Carlo simulation to demonstrate the possiblilty of the proposed method. The reconstructed image qualities were quantitatively evaluated in sense of the root mean square error (RMSE) and the peak signal-to-noise ratio (PSNR). Our simulation results indicate that the proposed method provides more accurate location information of the simulated gamma source than the CC-based method.

• 센서학회지
• /
• 제27권6호
• /
• pp.362-367
• /
• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.