• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.9
• /
• pp.1582-1589
• /
• 2006

A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. %is paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The nv mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.11
• /
• pp.34-43
• /
• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.61-69
• /
• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.4B
• /
• pp.298-305
• /
• 2003

In this paper, we proposed a high performance lookup controller for IP packet forwarding engine of ATM based label edge routers. The lookup controller is designed to provide services such as MPLS, VPN, ELL, and RT services as well as the best effort. For high speed searching for IP addresses, we employed a TCAM based hardware search device not using traditional algorithmic approaches. We also implement lookup control functions into FPGA for fast processing of packet header and lookup control. The proposed lookup controller is designed to support differenciated services for users and to process in pipelined mechanism for performance improvement. A two-step search scheme is also applied to perform lookup for the key combined with multi-field of packet header. We found that the proposed lookup controller provides the performance of about 16M packets per second through simulations.

• Journal of the Korea Computer Industry Society
• /
• v.3 no.3
• /
• pp.321-330
• /
• 2002

A 2-D median filter has many applications in various image and video signal processing areas. The rapid development in VLSI technology makes it possible to implement a real-time or near real-time 2-D median filter with reasonable cost. For the efficient VLSI implementation, the algorithm should have characteristics such as small memory requirements, regular computations, and local data transfers. This paper presents an architecture of the real-time two-dimensional separable median filter which has appropriate characteristics for the VLSI implementation. For the efficient two-dimensional median filter, a separable two-dimensional median filtering structure and a bit-sliced pipelined median searching algorithm are used. A behavioral simulator is implemented with C language and used for the analysis of the presented architecture.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.1-6
• /
• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.

• Journal of KIISE:Computing Practices and Letters
• /
• v.9 no.1
• /
• pp.1-12
• /
• 2003

Recently, many researches into distributed processing on Internet, and multimedia data processing have been performed. Rapid and convenient multimedia services supplied with high quality and high speed are to be needed. In this paper, we design and implement clip-based video retrieval system on the Web enviroment in real-time. Our system consists of the content-based indexing system supporting convenient services for video content providers, and the Web-based retrieval system in order to make it easy and various information retrieval for users in the Web. Three important methods are used in the content-based indexing system, key frame extracting method by dividing video data, clip file creation method by clustering related information, and video database construction method by using clip unit. In Web-based retrieval system, retrieval method ny using a key word, two dimension browsing method of key frame, and real-time display method of the clip are used. In this paper, we design and implement the system that supports real-time display method of the clip are used. In this paper, we design and implement the system that supports real-time retrieval for video clips on Web environment and provides the multimedia service in stability. The proposed methods show a usefulness of video content providing, and provide an easy method for serching intented video content.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.1
• /
• pp.178-184
• /
• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.271-274
• /
• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.