• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.704-712
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• 2016

Recently, the installation of photovoltaic (PV) systems has been increasing due to the worldwide interest in eco-friendly and infinitely abundant solar energy. However, the output power of PV systems is highly influenced by the surrounding environment. For instance, a string of PV systems composed of modules in series may become inoperable under cloudy conditions or when in the shade of a building. In other words, under these conditions, the existing control method of PV systems does not allow the string to be operated in the normal way, because its output voltage is lower than the operating range of the grid connected inverter. In order to overcome this problem, we propose a new control method using a DC-DC voltage regulator which can compensate for the voltage of each string in the PV system. Also, based on the PSIM S/W, we model the DC-DC voltage regulator with constant voltage control & MPPT (Maximum Power Point Tracking) control functions and 3-Phase grid connected inverter with PLL (Phase-Locked Loop) control function. From the simulation results, it is confirmed that the present control method can improve the operating efficiency of PV systems by compensating for the fluctuation of the voltage of the strings caused by the surrounding conditions.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1640-1646
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• 2013

Conventional power conversion unit that is a major part of the propulsion system has applied GTO thyristor as a switching semiconductor device of main circuit since introduction of the 8200 electric locomotive. But problem that quick maintenance is difficult and its cost is increasing occurs because major components of the power conversion unit are slowly discontinued. To solve these, in this paper, it was analyzed the response characteristic of the propulsion system modeling of the 8200 electric locomotive using IGBT which is applied recently to ensure propulsion control technology. As results of response for a Propulsion system modeling, it show that a power conversion unit is controlled by PLL(Phase-locked loop) and SVPWM(Space Voltage PWM) respectively.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1375-1386
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• 2016

To decouple the secondary saliencies in sensorless permanent magnet synchronous machine (PMSM) drives, a repetitive control (RC) in the angle domain is proposed. In this paper, the inductance model of a concentrated windings surface-mounted PMSM (cwSPMSM) with strong secondary saliencies is developed. Due to the secondary saliencies, the estimated position contains harmonic disturbances that are periodic relative to the angular position. Through a transformation from the time domain to the angle domain, these varying frequency disturbances can be treated as constant periodic disturbances. The proposed angle-domain RC is plugged into an existing phase-locked loop (PLL) and utilizes the error of the PLL to generate signals to suppress these periodic disturbances. A stability analysis and parameter design guidelines of the RC are addressed in detail. Finally, the proposed method is carried out on a cwSPMSM drive test-bench. The effectiveness and accuracy are verified by experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1709-1717
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• 2015

In remote islands PV (Photo Voltaic) panel with BESS (Battery Energy Storage System) supplies electric power to the customers in parallel operation with EG (Engine Generator) to save fuel consumption and to mitigate environmental load. BESS operates in voltage control mode when it supplies power to the load alone, while it operates in current control mode when it supplies power to the load in parallel with EG. This paper proposes a smooth mode change scheme from current control to voltage control of BESS by adding proper initial value to the integral part of voltage control, and a smooth mode change scheme from voltage control to current control by tracking the EG output voltage to the BESS output voltage using PLL (Phase-Locked Loop). The feasibility of proposed schemes was verified through computer simulations with PSCAD/EMTDC, and the feasibility of actual hardware system was verified by experiments with scaled prototype. It was confirmed that the proposed schemes offer a seamless operation in the stand-alone power system in remote islands.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2485-2488
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• 2003

본 논문에서는 DSP를 이용하여 운동하는 물체의 회전량을 측정하는 실린더형 진동 자이로스코프(이하 자이로) 제어기를 개발하였다. 진동 자이로를 구동하기 위해서는 정밀 진동제어와 신호 처리와 같은 고급 제어 기술이 필요하다. 정밀진동제어는 진동 자이로를 구동하기 위해 필요한 핵심기술로써 기존의 PLL(phase-locked loop)방식은 외부환경에 민감하여 구현이 까다로울 뿐만 아니라 자이로 개개의 고유 진동수가 다르기 때문에 대량 생산에 어려움이 있었다. 또한 자이로 출력 신호로부터 회전량을 검출하기 위해서는 진폭과 당향성 검출의 본 회로뿐만 아니라 잡음 제거와 신호 증폭, 온도 보상과 같은 전처리 과정도 필요하다. 본 논문에서는 DSP를 통해 정밀 진동제어와 잡음 제거, 방향성 검출 등의 기능들을 구현하였으며 증폭과 진폭(회전량) 검출은 아날로그 회로를 이용하였다. 또 한 외부와의 인터페이스를 위해 D/A 회로를 설계하였고 이들을 실험을 통해 검증하였다.

• Journal of IKEEE
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• v.15 no.2
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.190-192
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• 2007

본 논문에서는 새로운 FFT에 의한 계통위상 추정 알고리즘을 제안한다. 신재생 에너지 분야에 적용되는 계통연계형 인버터에서는 계통과 동기를 위해서는 반드시 계통의 위상 정보가 필요하다. 일반적으로 사용하는 3상 D-Q 변환에 의한 위상 추종과 달리 새롭게 제안하는 FFT를 사용하는 알고리즘은 게인 튜닝 부분이 없으며 FFT의 특성상 기본주파수 이외의 성분을 제외한 강력한 노이즈 제거효과로 인해 직접적이며 노이즈에 강한 특징을 가지고 있다. 시뮬레이션과 실험을 통하여 제안한 알고리즘의 성능이 만족할 만한 성능을 얻을 수 있음을 보였다.