• Title/Summary/Keyword: peak to average power ratio (PAPR)

Search Result 243, Processing Time 0.016 seconds

A Study on PAR Improvement of OFDM system using SLM-PTS Combine Method and ETD-Turbo Code (SLM-PTS 결합기법 및 ETD-Turbo부호를 적용한 OFDM 시스템에서의 PAR 개선에 관한 연구)

  • Sung Tae-Kyung;Kim Dong-Seek;Cho Hyung-Rae
    • Journal of Navigation and Port Research
    • /
    • v.29 no.8 s.104
    • /
    • pp.755-761
    • /
    • 2005
  • In this paper, we propose a high-speed adaptive PTS method which eliminates high PAR (Peak-to-Average Power Ratio) and we compare the proposed method with other conventional methods. In addition, we have designed a combined type SLM-PTS scheme to reduce PAR and evaluate the performance. The system used for evaluating PAR performance can be constructed as COFDM (Coded Orthogonal Frequency Division Multiplexing) applying ETD(Enhabced Time Diversity)-Turbo coding scheme. All the analyses in this paper are focused on the system characteristics according to IFFT's point and modulation method and the performance evaluation are based on the PAR reduction rates. As a result, the SLM-PTS combination method reveals good PAR reduction rate and remarkable reduction in the amount of calculations. Especially, in the case of combine-3 scheme, we can achieve approximately $3.7\~3.9$ dB PAR reduction on a basis of 10-5 BER level. Moreover, we can eliminate the side information in COFDM system because of its adaptive characteristics in evaluating PAR reduction rate, so that the additional errors can be omitted.

Noise Whitening Decision Feedback Equalizer for SC-FDMA Receivers (SC-FDMA 수신기를 위한 잡음 백색화 판정궤환 등화기)

  • Lee, Su-Kyoung;Park, Yong-Hyun;Seo, Bo-Seok
    • Journal of Broadcast Engineering
    • /
    • v.16 no.6
    • /
    • pp.986-995
    • /
    • 2011
  • In this paper, we propose a noise whitening decision feedback equalizer for single carrier frequency division multiple access (SC-FDMA) receivers. SC-FDMA has the same advantage as that of orthogonal frequency division multiple access (OFDMA) in which the multipath effect can be removed easily, and also solves the problem of high peak to average power ratio (PAPR) which is the main drawback of OFDMA. Although SC-FDMA is a single carrier transmission scheme, a simple frequency domain linear equalizer (FD-LE) can be implemented as in OFDMA, which can dramatically reduce the equalizer complexity. Moreover, some residual intersymbol interference in the output of the FD-LE can be further removed by an additional nonlinear decision feedback equalizer (DFE) in time domain, because the time domain signal is a digitally modulated symbol. In the conventional DFE, however, the noise is not white at the input of the decision device and correspondingly the decision is not optimum. In this paper, we propose an improved DFE scheme for SC-FDMA systems where a linear noise whitening filter is inserted before the decision device of the conventional DFE scheme. Through computer simulations, we compare the bit error rate performance of the proposed DFE scheme with the conventional equalizers.

A Fully Digital Automatic Gain Control System with Wide Dynamic Range Power Detectors for DVB-S2 Application (넓은 동적 영역의 파워 검출기를 이용한 DVB-S2용 디지털 자동 이득 제어 시스템)

  • Pu, Young-Gun;Park, Joon-Sung;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.9
    • /
    • pp.58-67
    • /
    • 2009
  • This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.