• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.523-524
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• 2007

This paper discusses the planarization process of thick copper film structure used for power supply device. Chemical mechanical polishing(CMP) has been used to remove a metal film and obtain a surface planarization which is essential for the semiconductor devices. For the thick metal removal, however, the long process time and other problems such as dishing, delamination and metal layer peeling are being issued, Compared to the traditional CMP process, Electro-chemical mechanical planarization(ECMP) is suggested to solve these problems. The two-step process composed of the ECMP and the conventional CMP is used for this experiment. The first step is the removal of several tens ${\mu}m$ of bulk copper on patterned wafer with ECMP process. The second step is the removal of residual copper layer aimed at a surface planarization. For more objective comparison, the traditional CMP was also performed. As an experimental result, total process time and process defects are extremely reduced by the two-step process.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.83-89
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• 2015

In this paper, we propose a fabrication technique for enhanced electrical properties of piezoelectric thick films with excellent patterning property using sol-infiltration and a direct-patterning process. To achieve the needs of high-density and direct-patterning at a low sintering temperature (< $850^{\circ}C$), a photosensitive lead zirconate titanate (PZT) solution was infiltrated into a screen-printed thick film. The direct-patterned PZT films were clearly formed on a locally screen-printed thick film, using a photomask and UV light. Because UV light is scattered in the screen-printed thick film of a porous powder-based structure, there are needs to optimize the photosensitive PZT sol infiltration process for obtaining the enhanced properties of PZT thick film. By optimizing the concentration of the photosensitive PZT sol, UV irradiation time, and solvent developing time, the hybrid films prepared with 0.35 M of PZT sol, 4 min of UV irradiation and 15 sec solvent developing time, showed a very dense with a large grain size at a low sintering temperature of $800^{\circ}C$. It also illustrated enhanced electrical properties (remnant polarization, $P_r$, and coercive field, $E_c$). The $P_r$ value was over four times higher than those of the screen-printed films. These films integrated on silicon wafer substrate could give a potential of applications in micro-sensors and -actuators.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.173-173
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• 2010

Recently, a patterned sapphire substrate (PSS) has been intensively used as one of the effective ways to reduce the dislocation density for the III-nitride epitaxial layers aiming for the application of high-performance, especially high-brightness, light-emitting diodes (LEDs). In this paper, we analyze the growth kinetics of the atoms and crystalline quality for the undopped-GaN depending on the facets of the pattern fabricated on a sapphire substrate. The effects of the PSS on the device characteristics of InGaN/GaN LEDs were also investigated. Several GaN samples were grown on the PSS under the different growth conditions. And the undoped-GaN layer was grown on a planar sapphire substrate as a reference. For the (002) plane of the undoped-GaN layer, as an example, the line-width broadening of the x-ray diffraction (XRD) spectrum on a planar sapphire substrate is 216.0 arcsec which is significantly narrower than that of 277.2 arcsec for the PSS. However, the line-width broadening for the (102) plane on the planar sapphire substrate (363.6 arcsec) is larger than that for the PSS (309.6 arcsec). Even though the growth parameters such as growth temperature, growth time, and pressure were systematically changed, this kind of trend in the line-width broadening of XRD spectrum was similar. The emission wavelength of the undoped-GaN layer on the PSS was red-shifted by 5.7 nm from that of the conventional LEDs (364.1 nm) under the same growth conditions. In addition, the intensity for the GaN layer on the PSS was three times larger than that of the planar case. The spatial variation in the emission wavelength of the undoped-GaN layer on the PSS was statistically ${\pm}0.5\;nm$ obtained from the photoluminescence mapping results throughout the whole wafer. These results will be discussed in terms of the mixed dislocation depending on the facets and the period of the patterns.