• Journal of applied mathematics & informatics
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• 제41권6호
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• pp.1317-1326
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• 2023

Today's computers, desktops and laptops were build with multi-core architecture. Developing and running serial programs in this multi-core architecture fritters away the resources and time. Parallel programming is the only solution for proper utilization of resources available in the modern computers. The major challenge in the multi-core environment is the designing of parallel algorithm and performance analysis. This paper describes the design and performance analysis of parallel algorithm by taking the Knight Tour problem as an example using OpenMP interface. Comparison has been made with performance of serial and parallel algorithm. The comparison shows that the proposed parallel algorithm achieves good performance compared to serial algorithm.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.63-68
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• 2022

In this study, we produced defect detection models using parallel convolution neural networks. If convolution neural networks are constructed parallel type, the model's detection accuracy will increase and detection time will decrease. We produced parallel-type defect detection models using 4 types of convolutional algorithms. The performance of models was evaluated using evaluation indicators. The model's performance is detection accuracy and detection time. We compared the performance of each parallel model. The detection accuracy of the model using AlexNet is 97 % and the detection time is 0.3 seconds. We confirmed that when AlexNet algorithm is constructed parallel type, the model has the highest performance.

• 한국정보처리학회논문지
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• 제6권4호
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• pp.901-915
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• 1999

분산 메모리 병렬 컴퓨터의 성능을 충분히 활용하고 프로그래밍의 난이도아 기종간 프로그램의 호환성을 해결하기 위하여 시스템 독립적이고 쉽게 프로그래밍 할 수 있는 데이터 병렬 언어에 대한 연구가 최근에 활발히 진행되고 있다. 대표적인 데이터 병렬 언어인 HPF 컴파일러는 사용자가 정의한 정보를 이용하여 데이터와 연산을 프로세서에 분할하여 할당하고, 메시지 패싱을 생성하는 기능을 제공함으로써 프로그램 작성자에게 전역 주소 공간을 이용하여 병렬 프로그램을 쉽게 개발 할 수 있는 기반을 제공한다. 본 논문에서는 데이터 종속성 분석, 데이터 및 연산 분할과 메시지 패싱 코드 생성의 4단계를 통하여, HPf 입력 프로그램을 MPI 메시지 패싱 코드가 삽입된 SPMD 프로그램으로 변환하는 HPF 병렬 프로그래밍 언어 변환기인 PPTran을 구현하고 그 성능을 검증한다.

• 대한기계학회논문집A
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• 제30권11호
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• pp.1447-1454
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• 2006

The evaluation of parallel performance of a high speed impact simulation is not an easy task because not only the development of parallel explicit code is difficult but also a large number of processors is not easily accessible. In this paper, the parallel performance of a new Lagrangian FEM impact code carried out on cluster supercomputer has been described in high speed range. In the case of metal sphere impacting to oblique plate, the overall speed-up continuously increases even up to 128 CPUs. Investigation of elapsed time of each part reveals that most of the inefficiency comes from the load imbalance of contact.

• ETRI Journal
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• 제44권2호
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• pp.313-326
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• 2022

This study presents a noble scheme for distributed and parallel simulations with optimized agent placement for simulation instances. The traditional parallel simulation has some limitations in that it does not provide sufficient performance even though using multiple resources. The main reason for this discrepancy is that supporting parallelism inevitably requires additional costs in addition to the base simulation cost. We present a comprehensive study of parallel simulation architectures, execution flows, and characteristics. Then, we identify critical challenges for optimizing large simulations for parallel instances. Based on our cost-benefit analysis, we propose a novel approach to overcome the performance constraints of agent-based parallel simulations. We also propose a solution for eliminating the synchronizing cost among local instances. Our method ensures balanced performance through optimal deployment of agents to local instances and an adaptive agent placement scheme according to the simulation load. Additionally, our empirical evaluation reveals that the proposed model achieves better performance than conventional methods under several conditions.

• 한국시뮬레이션학회논문지
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• 제2권1호
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• pp.31-44
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• 1993

Zeigler's DEVS(Discrete Event Systems Specification) formalism supports formal specification of discrete event systems in a hierarchical , modular manner. Associated are hierarchical, distributed simulation algorithms, called abstract simulators, which interpret dynamics of DEVS models. This paper deals with performance evaluation of P-DEVSIM ++, a parallel simulation environment which implements the DEVS formalism and associated simulation algorithms in a parallel environment. Performance simulator has been developed and used to experiment models of parallel simulation executions in different conditions. The experimental result shows that simulation time depends on both the number of processors in the parallel system and the communication overheads among such processors.

• 제어로봇시스템학회논문지
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• 제3권5호
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• pp.482-489
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• 1997

This paper presents the analysis of the kinematics and dynamics of redundant parallel manipulators, and provides design guides for advanced parallel mainpulators with high performance. Three types of redundancies are considered which include the redundancies in serial chain, joint actuation, and parallelism. First, the kinematic and dynamic models of a redundant parallel manipulator are obtained in both joint and Cartesian spaces, and the kinematic and dynamic manipulabilities are defined for the performance evaluation. The effects of the three types of redundancies on the kinematic and dynamic performance of a parallel manipulator are then analyzed and compared, providing a set of guides for the design of advanced parallel manipulators. Finally, the simulation results using planer parallel manipulators are given.

• 한국정보과학회논문지:시스템및이론
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• 제31권7호
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• pp.379-386
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• 2004

본 연구에서는 병렬프로그램을 효율적으로 개발할 수 있고 병렬처리 프로그램의 성능을 향상시키는 이식성을 갖는 고성능 병렬 라이브러리인 HPCL(High Performance Computing Library)을 구현하였다. HPCL은 C 언어와 Fortran 언어로 구현되었으며, Fortran 프로그램에서 메시지 전송 인터페이스인 MPI(Message Passing Interface)를 효율적으로 사용할 수 있도록 하였다. 성능 분석은 PC 클러스터와 상업용 슈퍼컴퓨터인 IBM SP4를 이용하여 병렬프로그램의 성능 향상 및 통신 오버헤드 등에 대하여 다양하게 이루어졌다.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.149-154
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• 2001

Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

• 한국정보통신학회논문지
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• 제14권1호
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• pp.138-144
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• 2010

최근에 도입되어 운영되고 있는 타키온 1차 시스템은 쿼드코어 AMD 바로셀로나 노드로 구성된 고성능 슈퍼컴퓨터이다. 본 논문에서는 하이브리드 병렬화 기법을 도입한 프로그램 중 하나로 사용되고 있는 멀티존(Multi-zone) NAS 병렬 벤치마크(NPB)를 이용하여 타키온 성능 및 병렬 확장성을 검증하고자 한다. 하이브리드 병렬 성능 시험을 위하여 NPB-3.3 버전 BT-MZ의 B 및 C클래스를 사용하였으며, 실제로 타키온 시스템의 1024개의 프로세스까지 병렬 확장성을 테스트를 하였다. 프로세서 1024개 이상 이용한 하이브리드 병렬컴퓨팅 계산 결과는 국내 최초이다. 이러한 하이브리드 병렬화 기법은 타키온처럼 멀티코어 기술을 적용한 고성능 컴퓨팅 시스템에서 매우 효율적이고 유용한 병렬 성능 벤치마크가 될 수 있음을 기술하였다.