• Journal of the Korea Society for Simulation
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• v.2 no.1
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• pp.31-44
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• 1993

Zeigler's DEVS(Discrete Event Systems Specification) formalism supports formal specification of discrete event systems in a hierarchical , modular manner. Associated are hierarchical, distributed simulation algorithms, called abstract simulators, which interpret dynamics of DEVS models. This paper deals with performance evaluation of P-DEVSIM ++, a parallel simulation environment which implements the DEVS formalism and associated simulation algorithms in a parallel environment. Performance simulator has been developed and used to experiment models of parallel simulation executions in different conditions. The experimental result shows that simulation time depends on both the number of processors in the parallel system and the communication overheads among such processors.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2003.04a
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• pp.521-528
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• 2003

This paper presents the results of a cooperative research on remote parallel pseudo-dynamic testing on a base-isolated bridge with multiple piers using Internet between KAIST, Korea and Kyoto Univ., Japan. Experimental facilities located at two institutions were parallelly used to test the nonlinear behavior of the base-isolators. Two data communication schemes for parallel tests were developed and the performance is compared. The results indicate that the elapsed time may vary widely depending on the data communication and testing schemes : i.e. 1-25sec for each time step. But it is fairly comparable with the time required for pseudo-dynamic testing. The testing method can become more powerful, as the data communication and monitoring techniques through Internet improve further.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.726-732
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• 2014

A current flowing through a distribution conductor produces induced voltage, which is harmful to a telecommunication line. Previous research on induced voltage has been focused on single-circuit lines in the distribution system. However, the double-circuit lines, referred to as parallel distribution lines, are widely used in distribution systems because they have significant economic and environmental advantages over single-circuit lines. Therefore, a study on the induced voltage in double-circuit lines is needed. This paper presents a method of calculating the induced voltage in a parallel distribution system using four-terminal parameters and vector analysis. The calculation method is verified by the Electromagnetic Transient Program (EMTP) simulation.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• Journal of Electrical Engineering and information Science
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• v.1 no.2
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• pp.15-26
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• 1996

MPAs(Massively Parallel Architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architecture faces problems of excessive synchronization overhead and inefficient execution of sequential programs while they offer the ability to exploit massive parallelism inherent in programs. In contrast, MPAs based on von Neumann computational model may suffer from inefficient synchronization mechanism and communication latency. DAVRID (DAtaflow/Von Neumann RISC hybrID) is a massively parallel multithreaded architecture which takes advantages of von Neumann and dataflow models. It has good single thread performance as well as tolerates synchronization and communication latency. In this paper, we describe the DAVRID architecture in detail and evaluate its performance through simulation runs over several benchmarks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.1
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• pp.50-57
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• 2011

In this paper, we proposes a new load-sharing algorithm with a ATmega2560 based digital communication. Proposed algorithm is different from conventional analog method. The high speed communication digital control is performed. To apply the digital communication and real-time control for time-sharing token bus method, we implemented high efficient load-sharing and redundancy. Also this system make down the price by auto ID algorithm and system response is improved by controller's voltage and current integral value sharing. In parallel system prototype, each module have controller and performed load-sharing according to master module integral value. In this paper, we verify the validity of proposed algorithm using PSIM program and prototype.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.13-16
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• 2005

It would be desirable to have methods for specific problems, which have low communication costs compared to the computation costs, and in specific applications, algorithms need to be developed and mapped onto parallel computer architectures. Main memory access for shared memory system or global communication in message passing system deteriorate the computation speed. In this paper, it is found that the m-step generalization of the block Lanczos method enhances parallel properties by forming m simultaneous search direction vector blocks. QR factorization, which lowers the speed on parallel computers, is not necessary in the m-step block Lanczos method. The m-step method has the minimized synchronization points, which resulted in the minimized global communications compared to the standard methods.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.