• KIPS Transactions on Computer and Communication Systems
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• v.4 no.7
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• pp.213-218
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• 2015

Given two strings X and Y (|X|=m, |Y|=n) over an alphabet ${\Sigma}$, the extended edit distance between X and Y can be computed using dynamic programming in O(mn) time and space. Recently, a parallel algorithm that takes O(m+n) time and O(mn) space using m threads to compute the extended edit distance between X and Y was presented. In this paper, we present an improved parallel algorithm using the shared memory on GPU. The experimental results show that our parallel algorithm runs about 19~25 times faster than the previous parallel algorithm.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.327-329
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• 2001

This paper presents the application of Parallel genetic algorithm and parallel tabu search to search an optimal solution of a unit commitment problem. The proposed method previously searches the solution globally using the parallel genetic algorithm, and then searches the solution locally using tabu search which has the good local search characteristic to reduce the computation time. This method combines the benefit of both method, and thus improves the performance. To show the usefulness of the proposed method, we simulated for 10 units system. Numerical results show the improvements of cost and computation time compared to previous obtained results.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.5
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• pp.147-152
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• 2015

In general, there are two synchronization methods in parallel event-driven simulation, pessimistic approach and optimistic approach. In this paper, we propose a new approach, sporadic synchronization combining both for prediction-based parallel event-driven logic simulation. We claim this hybrid solution is pretty effective to minimize both checkpoint overhead and restart overhead, which are related problems with frequent false predictions for improving the performance of the prediction-based parallel event-driven logic simulation. The experiment has clearly shown the advantage of the proposed approach.

• 한국전산유체공학회:학술대회논문집
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• 2006.05a
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• pp.335-338
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• 2006

• International journal of advanced smart convergence
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• v.8 no.4
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• pp.194-199
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• 2019

As the performance of the system increases, more parallelized data is being processed than single processing of data. Today's cpu structure has been developed to leverage multicore, and hence data processing methods are being developed to enable parallel processing. In recent years desktop cpu has increased multicore, data is growing exponentially, and there is also a growing need for data processing as artificial intelligence develops. This neural network of artificial intelligence consists of a matrix, making it advantageous for parallel processing. This paper aims to speed up the processing of the system by using raspberrypi to implement the cluster building and parallel processing system against the backdrop of the foregoing discussion. Raspberrypi is a credit card-sized single computer made by the raspberrypi Foundation in England, developed for education in schools and developing countries. It is cheap and easy to get the information you need because many people use it. Distributed processing systems should be supported by programs that connected multiple computers in parallel and operate on a built-in system. RaspberryPi is connected to switchhub, each connected raspberrypi communicates using the internal network, and internally implements parallel processing using the Message Passing Interface (MPI). Parallel processing programs can be programmed in python and can also use C or Fortran. The system was tested for parallel processing as a result of multiplying the two-dimensional arrangement of 10000 size by 0.1. Tests have shown a reduction in computational time and that parallelism can be reduced to the maximum number of cores in the system. The systems in this paper are manufactured on a Linux-based single computer and are thought to require testing on systems in different environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3603-3609
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• 2011

In this paper, we proposes new load-sharing algorism for equal current division using CAN communication. Proposed algorithm is different from conventional analog method, it performed strong Load-sharing using bi-direction high speed communication. Each modules constitution on independence controller (voltage controller, electric current controller). In parallel system prototype, each module have controller and performed load-sharing according to master module integral value. Also additional controller use for getting each module situations that fault situation of module and fault locate of module. we implemented high efficient load-sharing and redundancy. In this paper, we verify the validity of proposed algorithm using PSIM program and prototype.

• Journal of Navigation and Port Research
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• v.28 no.10 s.96
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• pp.875-879
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• 2004

In this paper, sub-harmonic pumped(SHP) mixer using anti-parallel diode pair(APDP) is designed for 5 GHz band wireless communication system. Conventional mixers mix LO with RF, and obtain IF signal from the difference between LO and RF. As the frequency increase, LO signal requires higher LO power, better phase noise characteristics, more stable La. However, using APDP, the SHP mixer mixes the 2nd harmonics of LO signal. Therefore, the SHP mixer has an advantage that the LO signal frequency required for IF signal is reduced at half value of LO fundamental frequency. When LO power is 3 dBm, the conversion loss of manufactured SHP mixer is 12.83 dB. The isolation of LO/IF, 2LO/IF, RF/1F and LO/RF is 39.17 dB, 58 dB, 34 dB, and 67.9 dB. respectively. For this case, IP3 at input is 8 dBm.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.549-560
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• 2001

Cluster system provides attractive scalability in terms of compution power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive MPPs (massively parallel processors). Load balancing is very important issue since an inappropriate scheduling of tasks cannot exploit the true potential of the system and can offset the gain from parallelization. In parallel processing program, it is difficult to predict the load of each task before running the program. Furthermore, tasks are interdependent each other in many ways. The dynamic load balancing algorithm, which evaluates each processor's load in runtime, partitions each task into the appropriate granularity and assigns them to processors in proportion to their performance in cluster systems. However, if the communication cost between processing nodes is expensive, it is not efficient for all nodes to attend load balancing process. In this paper, we restrict a processor that attend load balancing by the communication cost and the deviation of its load from the average. We simulate various models of the cluster system with parameters such as communication cost, node number, and range of workload value to compare existing load balancing methods with the proposed dynamic algorithms.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.