• 제목/요약/키워드: packaging substrate

검색결과 438건 처리시간 0.03초

The Study of Low Temperature Firing Glass-Ceramics Substrate in Lithium Fluorhectorite

  • Choi, J-H;Park, D-H;Kim, B-I;Kang, W-H
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 1999년도 추계 기술심포지움 논문집
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    • pp.111-115
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    • 1999
  • The $Li_2O-MgO-MgF_2-SiO_2$glasses with addition of $B_2O_3$ were investigated in order to make glass-ceramics for low temperature firing substrate. Glasses were made by melting at $1450^{\circ}C$ in the electronic furnace and crystallized at $750^{\circ}C$. After the crystallization, crystal phases and microstructure were observed. The crystal phases were polycrystalline of lithium boron fluorphlogopite and lithium fluorhectorite. The crystal shape was changed to grande type from needle type with the increase in $B_2O_3$ contents. Average particle size of the glass-ceramics aftar water swelling was $3.77{\mu}{\textrm}{m}$. The optimum sintering temperature and sintering shrinkage of the substrate were $900^{\circ}C$ and 13.4vol%, respectively.

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Prediction Methodology for Reliability of Semiconductor Packages

  • Kim, Jin-Young
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 International Symposium
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    • pp.79-94
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    • 2002
  • Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

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단일이온교환 공정에 따른 기판유리의 특성 (Properties of Substrate Glass by Single ion Exchange Process)

  • 이회관;이용수;강원호
    • 마이크로전자및패키징학회지
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    • 제9권3호
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    • pp.25-29
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    • 2002
  • 단일이온교환 공정을 도입하여 평판디스플레이에 사용되는 기판유리를 대상으로 이온교환 거동 및 기계적 특성에 대하여 조사하였다. 효과분석으로는 온도와 시간 변화에 따른 $K^+$ 이온의 침투깊이, 이온교환량, 밀도, 열팽창계수를 관찰하였다. 기판유리의 기계적 특성으로는 3점 곡강도와 만곡변화를 관찰하였으며, 광학현미경을 사용하여 곡강도 측정 후 파괴된 시편의 형태를 조사하였다.

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LTCC 기판의 Particle Size 에 따른 Ag-Pd 전극의 Soldering 특성 변화 (Soldering characteristics of Ag-Pd electrodes in relationship to differing particle size of LTCC substrate)

  • 조현민;유명재;박종철
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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    • pp.130-133
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    • 2002
  • Solder leaching resistance of the metal electrode is an important factor with regard to adhesion properties of ceramic substrate. In the Low Temperature Co-fired Ceramics (LTCC), Ag-Pd or Ag-Pt pastes are used instead of pure Ag paste to prevent leaching. Solder leaching behavior of the Ag-Pd paste in relation to LTCC raw material powder size was investigated. First fabrication of LTCC green tape with different particle size was done. LTCC substrates with Ag-Pd electrode were prepared using conventional multilayer ceramic process. Dipping test was performed to test solder leaching behavior of the electrode. Ag-Pd electrode on LTCC substrate with smaller particle size achieved higher solder leaching resistance.

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The Fabrication of Low Temperature Firing Substrate of $Li_2O-MgO-MgF_2-SiO_2-B_2O_3$ system

  • Park, Jung-Houn;Park, Dae-Hyun;Kang, Won-Ho
    • 마이크로전자및패키징학회지
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    • 제6권4호
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    • pp.35-39
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    • 1999
  • The $Li_2O-MgO-MgF_2-SiO_2$glasses with addition of $B_2O_3$ were investigated in order to make glass-ceramics for low temperature firing substrate. Glasses were made by melting at $1450^{\circ}C$ in the electronic furnace and crystallized at $750^{\circ}C$. The crystal phases were polycrystalline of lithium boron fluorphlogopite and lithium fluorhectorite. The crystal shape was chanced to granule type from needle type with increasing $B_2O_3$ content. Average particle size of the glass-ceramics after water swelling was 3.77$\mu\textrm{m}$. The optimum sintering temperature and sintering shrinkage of the substrate were $900^{\circ}C$ and 13.4%, respectively.

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유기기판에 내장된 인덕터의 커플링을 이용한 광대역 LC 발룬의 설계 (Design of Inductive coupled wideband LC Balun Embedded Into Organic Substrate)

  • 박종철;박재영
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.1502-1503
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    • 2007
  • In this paper, inductive coupled LC balun has been desi gned and simulated for embedding into an organic packaging substrate. Inductive coupling method was applied to obtain wide band characteristics, and high dielectric film was utilized to reduce a size of the balun. The proposed balun has a novel scheme which consists of three embedded LC resonators with inductive coupling. This proposed balun has relatively small inductance and capacitance values which can be easily embedded into the organic packaging substrate. Furthermore, it has a good phase imbalance characteristic. The simulated results of proposed balun are an insertion loss of 1.2 dB, a return loss of 10 dB, a phase imbalance of 1 degree at frequency bandwidth of 750 MHz ranged from 1.8 GHz to 2.55 GHz, respectively. This balun has an area of $2mm{\tims}3.5mm{\times}0.66mm$ (height).

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적층 유기기판 내에 내장된 소형 LC 다이플렉서의 설계 및 제작 (Design and Fabrication of Miniaturized LC Diplexer Embedded into Organic Substrate)

  • 이환희;박재영;이한성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.262-263
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    • 2007
  • In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

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Impact of Copper Densities of Substrate Layers on the Warpage of IC Packages

  • Gu, SeonMo;Ahn, Billy;Chae, MyoungSu;Chow, Seng Guan;Kim, Gwang;Ouyang, Eric
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.59-63
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    • 2013
  • In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

Critical Cleaning Requirements for Flip Chip Packages

  • Bixenman, Mike;Miller, Erik
    • 마이크로전자및패키징학회지
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    • 제7권1호
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    • pp.61-73
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    • 2000
  • In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology.

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