• 한국전기전자재료학회논문지
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• 제22권8호
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• pp.625-631
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• 2009

In this thesis, lateral thermosonic bonding with ACFs was investigated as a process to make high reliability joints for FPD fabrication. Conditions for thermosonic and thermocompression bonding with ACFs were determined and used to make specimens in a driving test jig for testing of bond reliability by thermal shock. The results showed that thermosonic bonding temperature of $199\;^{\circ}C$ and bonding time of 1s produced bonds with good reliability. Additionally, thermosonic bonding temperature and time were reduced and thermal shock test results compared to this proposed curing condition. It is concluded that theromosonic bonding with ACFs can be effectively applied to reduce bonding temperature and time compared with that of thermocompression bonding.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집A
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• pp.138-143
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• 2001

To perform the rigorous integrity evaluation of RPV, it is necessary to consider metallurgical factors such as microstructure evolution during multi-pass welding process and PWHT. The microstructures of the heat affected zone(HAZ) of SA508 steel were predicted by a combination of simulated thermal analysis and a simple kinetic models for austenite grain growth and austenite-ferrite transformation. Phase equilibrium of SA508 steel were calculated using a Thermo-Calc package. Carbide growth in th HAZ were predicted by a empirical model, taking into account the predicted microstructure evolution.

• Journal of Radiation Protection and Research
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• 제34권3호
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• pp.144-150
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• 2009

This study examines how much the radiation dose rate around it varies if a crack occurs on the spent nuclear fuel rod. The spent nuclear fuel rod to be examined is that of Kori unit 3&4. The source terms are evaluated using the ORIGEN-ARP that is part of the version 5.1 of the SCALE package. The radiation dose rate is assessed using the TORT. To check if the structure of a fuel rod is appropriately modeled in the TORT calculation, the calculation results by the TORT are compared with those by the ANISN for the same case. From the code simulation, it is known that if a crack occurs on the spent nuclear fuel rod, the neutron dose rate varies depending on what material is the crack filled with, but the gamma dose rate varies irrespective of type of the material that the crack is filled with.

• Nuclear Engineering and Technology
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• 제40권6호
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• pp.511-516
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• 2008

Korea Hydro & Nuclear Power Co., Ltd. (KHNP) developed new IP-2 packages to transport low- and intermediate-level radioactive waste (LILW) steel drums from nuclear power plants to a disposal facility in accordance with IAEA and Korean transport regulations of radioactive material. Radiation shielding evaluation of the packages was carried out to demonstrate compliance with the regulatory requirements for IP-2 packages of radioactive material. Dose rate limits of LILW drums contained in the packages were determined.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.348-348
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• 2008

In recent, the concept of system-on-package (SOP) for highly integrated multifunctional systems has been paid attention to for the miniaturization and high frequency of electronic devices. In order to realize SOP, co-integration of passive devices, such as capacitors, resistors and inductors, and active devices should be achieved. If ceramic thick films can be grown at room temperature, we expect to be able to overcome many problems in conventional fabrication processes. So, we focused on the aerosol deposition method (ADM) as room temperature fabrication technology. ADM is a novel ceramic coating method based on the Room Temperature Impact Consolidation (RTIC) phenomena. This method has a wide range potential for fabrication of co-integration of passive and active devices. In this paper, I will present the future potential of ADM introducing various ceramic dielectric thick films for the integration of electronic ceramics.

• 산업공학
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• 제5권1호
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• pp.35-46
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• 1992

This paper deals with analysis of material handling system efficiency of a heat-exchanger manufacturing line. This line is a typical flow shop type assembly line which consists of 10 steps of assembly stations. Each station have one or two workers who assemble and move components for the job, and no special transporters for component's movement. Therfore, all the workers are involoved in unnecessary moving activities which decrease overall production efficiencies of the line. To improve productivities, production outputs and worker's job performances for this assembly line, the several alternatives are considered such as installing new conveyor lines and automatic guided vehicle(AGV) system. Analyzing economic feasibilities and responses of the system alternatives, an experimental simulation model is built suing SIMAN Ver. 3. 5 simulation language with CINEMA package for animation of the process flow. Through this animation process a vivid picturial analysis could performed on the process flow.

• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.647-655
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• 2003

Commonly used SAW duplexers have a difficulty on manufacture so that a transmission line is printed on the package or an LTCC multi-layer is needed because a quarter-wave transmission line which is a kind of an isolation network is applied to the SAW duplexers. In this study, new structures of one chip type SAW duplexers are proposed. In the proposed structure, Tx and Rx SAW ladder filters and isolation networks are located on a single 36LiTaO$_3$ piezoelectric substrate. The manufacture process is very simple than commonly used product. It is possible to improve tile performance by means of optimizing the micro-strip line lumped elements. It is easy to integrate and modulate with other surrounding components. The optimal design techniques can be applied to other kind of multi-port devices.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.577-595
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• 2017

${\bullet}$ Silicon Carbide (SiC) had excellent material properties as the base material for next generation of power semiconductor. In developing SiC MOSFET, gate oxide reliability issues had to be first overcome before commercial application. Besides, a high and stable gate-source voltage threshold $V_{GS(th)}$ is also an important parameter for operation robustness. SiC MOSFET with such characteristics can directly use existing high-speed IGBT gate driver IC's. ${\bullet}$ The linear voltage drop characteristics of SiC MOSFET will bring lower conduction loss averaged over full AC cycle compared to similarly rate IGBT. Lower switching loss enable higher switching frequency. Using package with auxiliary source terminal for gate driving will further reduce switching losses. Dynamic characteristics can fully controlled by simple gate resistors. ${\bullet}$ The low switching losses characteristics of SiC MOSFET can substantially reduce power losses in high switching frequency operation. Significant power loss reduction is also possible even at low switching frequency and low switching speed. in T-type 3-level topology, SiC MOSFET solution enable three times higher switching freqeuncy at same efficiency.

• 한국전기전자재료학회논문지
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• 제15권4호
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• pp.344-348
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• 2002

As microelectronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important fort many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (s-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.