• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.104-113
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• 1994

We have fabricated n-p-n HBTs using 3-inchAlgaAs/GaAs hetero structure epi-wafers grown by MBE. DC and AC characteristics of HBT devices were measured and analyzed. For HBT epi-structure, Al composition of emitter was graded in the region between emitter cap and emitter. And base layer was designed with concentration of 1${\times}10^{19}/cm^{3}$ and thickness of 50nm, and Be was used as the p-type dopant. Principal processes for device fabrication consist of photolithography using i-line stepper, wet mesa etching, and lift-off of each ohmic metal. The PECVD SiN film was used as the inslator for the metal interconnection. HBT device with emitter size of 3${\times}10{\mu}m^{2}$ resulted in cut-off frequency of 35GHz, maximum oscillation frequency of 21GHz, and current gain of 60. The distribution of the ideality factor of collector and base current was very uniform, and the average values of off-set voltage and current was very uniform, and the average values of off-set voltage and current gain were 0.32V and 32 within a 3-inch wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.405-408
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• 1998

Due to the large conduction band discontinuity between emitter base, OmGaAs HBT has an advantge to enable the hot electrons to inject into the base. In this paper, InAlGaAs/InGaAs HBT with the various emitter junction gradings and the modified collectors are simulated and analyzed by HMC(hybrid monte carlo) simulator in order to find a optimal structure for the shortest transit time. A minium base transit time (.tau.$_{b}$ ) of 0.21 ps was obtained for HBT with the grading layer, which is parabolically graded from x=1.0 to x=0.5. The minimum collector transit time (.tau.$_{c}$ ) of 0.31ps was found when the collector was modified by inserting p$^{[-10]}$ and p$^{+}$ layers. Thus HBT in combination with the emitter grading and the modified collector layer showed the cut-off frequency (f$_{T}$) of 183GHz.z.z.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.1 s.24
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• pp.99-108
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• 2006

In this paper, we analyzed the characteristics of emitter geolocation coverage area within which the emitter lies with a specified probability based on the LOBs(Line of Bearing) of sensors. Stansfield and MSD algorithms were applied to calculate BPE(Best Point Estimate), EEP(Elliptical Error Probable) and CEP(Circular Error Probable), They used the weighting factors composed of ${\sigma}_{Phi}$ (bearing error), QF(quality factor), $P_{e}$ (probability being inside) to optimize the performance. The characteristics of EEP was investigated in the change of them and those of CEP was analyzed based on the deployment of sensors.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.213-216
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• 2001

The use of a thin film of indium between the ITO and the $n^{+}$-InP contact layers for InP/InGaAs HPTs was studied without degrading its excellent optical transmittance properties. ITO/$n^{+}$-InP ohmic contact was successfully achieved by the deposition of Indium and thermal annealing. The specific contact resistance of about 6.6$\times$$10^{-4}$$\Omega\textrm{cm}^2$ was measured by use of the transmission line method (TLM). However, as the thermal annealing was just performed to ITO/$n^{+}$-InP contact without the deposition of Indium between ITO and $n^{+}$-InP, it exhibited schottky characteristics. In the applications, the DC characteristics of InP/InGaAs HPTs with ITO emitter contacts was compared with that of InP/InGaAs HBTs with the opaque emitter contacts.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.123.1-123.1
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• 2011

기존의 p-type 태양전지 공정과 유사한 공정으로 제작되는 n-type $ALU^+$태양전지는 후면에 Al을 screen printing하여 emitter층을 형성한 구조이다. screen printing은 공정의 단순화와 제조 단가의 저비용으로 인해, metalization 공정에서 많이 쓰이고 있다. 본 연구에서는 양산 가능한 n-type $ALU^+$태양전지 제작을 위해, 후면 Al emitter 층을 single, dobule, triple로 변경하며 Al의 양을 가변하였고, 그에 따른 특성의 변화를 연구하였다. screen printing 횟수가 변경된 후면 Al emitter 층의 특성은 DIV와 LIV 측정을 통해 분석하였다. 실험 결과 Al을 single printing 하였을 때보다, double, triple printing을 통하여 Al의 양을 증가하였을 때, DIV 데이터에서 직렬저항(Rs)가 $24.44{\Omega}/cm^2$에서 $0.31{\Omega}/cm^2$으로 감소하였고, 단락전류(Jsc)는 1.26mA/$cm^2$에서 37.7mA/$cm^2$으로 약 300% 증가한 것을 확인할 수 있었다. 프린팅 횟수에 따른 LIV 데이터의 Fill Factor를 분석하게 되면, double printing이 64.35%로 54.75%의 triple printing보다 약 1.17배 더 향상된 것으로 확인하였다. 이러한 결과를 바탕으로 후면 Al emitter 형성시에 Al의 양이 적절하지 못한 이유로, Al emitter가 제대로 형성되지 못하거나 과하게 형성되면, 태양전지 내부에 누설 저항의 변화와 누설 전류의 증가로 인해, 단락전류(Jsc)와 Fill Factor 감소의 주요 원인이 된다는 것을 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.233-233
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• 2010

It is important to form the n+ emitter layer for generating electric potential collecting EHP(Electron-Hole Pair). In this paper the formation on the n+ emitter layer of silicon wafer has been made with respect to uniformity of shallow diffusion from a liquid source. The starting material was crystalline silicon wafers of resistivity $0.5{\sim}3\{Omega}{\cdot}cm$, p-type, thickness $200{\mu}m$, direction[100]. The formation of n+ emitter layer from the liquid $POCl_3$ source was carried out for $890^{\circ}C$ in an ambient of $N_2:O_2$::10:1 by volume. And than each conditions are pre-deposition and drive-in time. It has been made uniformity of at least. so, the average of sheet resistance was about 0.12%. In this study, sheet resistance was measured by 4-point prove.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.410-414
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• 2013

Rapid thermal processing (RTP) abruptly decreases the time required to perform solar cell processes. RTP were used to form emitter of crystalline silicon solar cells. The emitter sheet resistance is studied as a function of time and temperature. The objective of this study is reduction of doping process time with same performance. Emitter difRapid thermal dfusion was carried out by using a spin on doping and a RTP. iffusion was performed in the temperature range of $700{\sim}750^{\circ}C$ for 1m 30s~15 m. Thermal budgets yielded a $50{\Omega}/sq$ emitter using a P509 source. To reduce process time and get high efficiency, rapid thermal diffusion by IR lamp was employed in air atmosphere at $700^{\circ}C$ for 15 m.

• Current Photovoltaic Research
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• v.1 no.1
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• pp.17-26
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• 2013

In contrast to conventional crystalline cells, back-contact solar cells feature high efficiencies, simpler module assembly, and better aesthetics. The highest commercialized cell and module efficiency was recorded by n-type back-contact solar cells. However, the mainstream PV industry uses a p-type substrate instead of n-type due to the high costs and complexity of the manufacturing processes in the case of the latter. P-type back-contact solar cells such as metal wrap-through and emitter wrap-through, which are inexpensive and compatible with the current PV industry, have consequently been developed. In this paper the characteristics of EWT (emitter wrap-through) solar cells and their status and prospects for development are discussed.