• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.10
• /
• pp.885-892
• /
• 2013

The main advantage of ESPAR antenna is that ESPAR antenna requires only a single RF chain for reduction of transceiver's hardware complexity, as compared to conventional MIMO system. In conventional MIMO system, each data symbol is mapped to each antenna. But, each data symbol is mapped to each orthogonal basis pattern in ESPAR antenna system. In this paper, we design beamspace MIMO system using ESPAR antenna with single RF chain for MIMO system of low-complexity and low power consumption. And then, we analyze performance of beamspace MIMO according to each PSK modulation. Performance of beamspace MIMO system is similar to performance of conventional MIMO system. As a result of analyzing the performance of beamspace MIMO system using higher-order PSK modulation. we can confirm that performance characteristic of beamspace MIMO system with low complexity and low power consumption is similar to digital communication of signal domain.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.7
• /
• pp.768-773
• /
• 2012

A branch-line hybrid using microstrip artificial transmission lines(ATLs) with slotted-triangular patches is proposed. The proposed artificial transmission line is compact in structure as well as easy to adjust the characteristic impedance and electrical length of equivalent transmission line by changing the slot's parameters; hence, it is useful for miniaturizing conventional transmission lines. The designed branch-line hybrid, because of the use of the right angled isosceles triangular shaped artificial transmission lines as building blocks, has no useless empty space, and hence optimally miniaturized. A fabricated 3 dB branch-line hybrid shows the coupling variation of ${\pm}0.5$ dB and the phase difference between two output ports of $91^{\circ}{\pm}4^{\circ}$ within 15 % bandwidth at 2.45 GHz center frequency. The size of proposed branch-line hybrid is only 38% of the conventional branch-line hybrid.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.3
• /
• pp.317-323
• /
• 1998

A synchronization is important element not only wire communication but also wireless communication. Especially, In SS(Spread Spectrum) communication method used GPS(Global Positioning System) synchronization is more important. A synchronous oscillator(SO) is a network which synchronizes, tracks, filter, amplifies and divides (if necessary) in a single process. Without an input signal, the SO is a free-running oscillator, oscillating at a frequency $w_0$, but phase changes $180^{\circ}$ within tracking range of SO. Therefore CPSO was used for this problem. The coherent phase synchronous oscillator(CPSO) is created by adding two external loops to the SO and has a wider tracking bandwidth and a zero-offset phase response (coherent) while maintaining the SO properties of high signal-to-rejection and fast frequency acquisition times. Therefore phase between input signal and output signal is synchronized. In this paper, GPS data recovery circuit has applied CPSO using front reference characters and has certified an excellent data recovery capability.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.5
• /
• pp.1015-1022
• /
• 2012

This paper deals with hardware design which unifies MD5 and HAS-160 hash algorithms. Two algorithms get a message with arbitrary length and process message blocks divided into 512 bits each time and output a hash code with a fixed length. MD5 ouputs a hash code of 128 bits and HAS-160 a hash code of 160 bits. The unified hash core designed has 32% of slices overhead compared to HAS-160 core. However, there is only a fixed message buffer space used. The unified hash core which run a step in one clock cycle operates at 92MHz and has performance which digests a message in the speed of 724Mbps at MD5 and 581Mbps at HAS-160 hash mode. The unified hash core which is designed can be applicable to the areas such as E-commerce, data integrity and digital signature.

• The KIPS Transactions:PartA
• /
• v.17A no.2
• /
• pp.63-72
• /
• 2010

Recently, the need for multimedia devices, such as digital TV, and camcorder has increased. These devices provide many services on multimedia files such as playing, recording, and editing. Throughout these services, in case of storing edited large-scaled multimedia files, existing file system have several capability problems that are taking too much time and requiring disk I/O. In this paper, we propose the use of Linux Ext2 file system based 'Block-Link file (BL-file) system' in order to solve these problems. For the BL-file system, when editing and storing large-scaled files, there is no data input or output but only modification of the metadata. Additionally, by sharing data blocks between multimedia files, we can save disk spaces. Moreover, because the managing of data block sharing information is more convenient than the existing FWAE technique, we can lessen system overhead. The BL-file system is based on Ext2 file system and implemented in a Linux environment, and the usefulness of the proposed technique is validated by applying the Linux multimedia file-editing tool 'Avidemux'.

• Journal of the Institute of Convergence Signal Processing
• /
• v.5 no.2
• /
• pp.159-164
• /
• 2004

This paper proposes a new digital filter implementation which adopts an identical structure at both behavioral and logic level in top-down design. This methodology is based on the observation that multiplication is a form of convolution and carrying, and therefore multiplication is implemented with the same structure as that of a convolution in a recursive manner at the logic level. In order to demonstrate a recursive structure-based FIR digital filter, we select L-tap transposed and systolic FIR filters, and implement them to have a single structure. The proposed filter design becomes regular and modular because of the recursive adoption of a single structure for convolutions, and is very compact in that it needs only two 1-bit I/O ports in addition to significant improvement on hardware complexity without time penalty on the output sequence.

• Journal of Information Technology and Architecture
• /
• v.9 no.1
• /
• pp.111-120
• /
• 2012

Many Countries are recently focued on building capability based military and operating for the defense budget efficiency and operational effectiveness. The EA not only defines enterprise scope but also identifies relation among them, manage change and complexity. Accordingly, this research aims to build architecture framework which can achieve alignment, integration and interoperability by developing it with output. Through this, architecture framework can be changed into force development and operation. And it can be used for construction of effective force and operation for NCO by applying mathematical model and method of force priority development based on developed capabilities-based architecture framework.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.1
• /
• pp.14-24
• /
• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.788-791
• /
• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.8
• /
• pp.1776-1782
• /
• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.