• 전기전자학회논문지
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• 제11권1호통권20호
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.457-458
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• 2008

This paper presents an output common mode current compensation method to achieve both constant Gm and constant gain. A conventional rail-to-rail CMOS op-amp with constant Gm was designed by using complementary differential input stage and current compensation skills. But it doesn't operate constant gain, because of output resistance variation. With $0.18{\mu}m$ CMOS process, the simulation results show that the differential gain variation can achieve less than 1.3dB. And a 60dB gain, a 13.5MHz unity gain-frequency, and 1mW power consumption, when operating at 1.8V and 10pF load.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1117-1120
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• 2003

In this paper, a 1.5V CMOS high frequency operational amplifier for high frequency signal processing systems is presented. For obtaining the high gain and the high unity gain frequency with the 1.5V supply voltage, the op-amp is designed with simple two stages which are consisting of the rail-to-rail differential input stage and the class-AB output stage. The designed op-amp operates with the 1.5V supply voltage, and shows well the push-pull class-AB operation. The simulation results show the DC open loop gain of 77dB and the unity gain frequency of 100MHz for the 1㏁ ┃ 10pF load. When the resistive load R$_1$. is varied from 1㏁ to 1 ㏀, the DC open loop gain decreases by only 4dB.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.17-18
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• 2000

A low-power source driver for TFT-LCDs has been proposed using the triple charge sharing method that enhances the AC power saving efficiency of the prior charge sharing method. The AC power saving efficiency of the proposed source driver reaches 66.6%. In addition, a novel OP-AMP with low-quiescent current has been developed. The measured quiescent current of the OP-AMP is $5{\mu}A{\sim}7{\mu}A$ at VDD=5V and VSS=0V with load resistance of $2k{\Omega}$ and load capacitance of 300pF.

• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• 조명전기설비학회논문지
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• 제12권4호
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• pp.1-5
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• 1998

본 연구는 전자식 스타터를 사용하는 경우 형광햄프 수명말기에 발생되는 이상상태에서 회로를 보호할 수 있 는 보호회로에 대한 것이다. 본 논문에서는 이를 위하여 OP AMP와 SSR을 사용한 보호회로를 제시하였다. 제안된 회로를 PSpice를 사용하여 시뮬레이션올 수행하였으며, 이를 실험결과와 비교하여 그 타당성올 입증하였다.

• 한국통신학회논문지
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• 제7권1호
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• pp.29-36
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• 1982

L.T.Bruton에 의해 提案된 FDNR(frequency dependent negative resistance)의 槪念이 周波數選擇性을 갖는 回路綱의 能動化에 有利함을 고찰하였다. 그리고 하나의 OP-Amp을 使用한 새로운 FDNR을 提案함으로써 回路의 簡單化를 이룩하였다. 또한 提案된 FDNR을 能動elliptic 領域filter에 적용하고 設計된 回路의 周波數特性을 實驗을 통하여 確認함으로써 그 合當性을 立證하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.27-30
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• 2003

Wireless power transmission system is one of the very interesting field not only in a technical and economical point of view but also that people are still trying to realize lossless power transmission. This paper has a purpose on the efficient power transmission at the passive type ICcard by using wireless power transmission system. The most difficult but important part of the passive type RF-ID system is building the system that supplies power from Reader-antenna to IDcard-antenna. To check what is the most efficient way to deliver power depending on what kind of specifications of the power-amp in reader, antenna and antenna in IDcard is for operating IDcard circuit efficiently receiving the power from reader-antenna. For this, we used 125kHz sinewave for RF signal as a basic specification, power-amp : OP-Amp for amplifying signal and AB Class push-pull power-amp for amplifying power, loop type antenna.

• 동의생리병리학회지
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• 제28권2호
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• pp.195-199
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• 2014

Although the Herba Cirsii is known to posses beneficial health effects, the anti-diabetic effects and the mechanism of action have not been elucidated. In the present study we have shown that Herba Cirsii Extract (HCE) can stimulate glucose uptake in OP9 adipocytes. Unlike insulin, HCE did not stimulate the Ser473 phosphorylation and activation of Akt. The increasing effects of HCE on glucose uptake were inhibited by PD680509 and compound C pretreatment, which means that the glucose uptake effects by HCE were carried out by extracelluar signal-regulated kinase1/2(ERK1/2) and AMP-activated protein kinase (AMPK) activation. Further studies revealed that HCE stimulated glucose transport occurs through a mechanism involving ERK1/2 activation and AMPK activation.

• 한국전자파학회논문지
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• 제22권6호
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• pp.641-647
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• 2011

본 논문은 0.5~2.0 GHz에서 -70~0 dBm의 동적 범위를 갖는 로그 비디오 증폭기(Successive Detecting Log Video Amplifier, 이하 SDLVA)를 설계 및 제작하였다. 제작된 SDLVA는 5단의 증폭기를 이용한 고주파 출력부, 2단의 로그검파기 그리고 선형성 개선을 위하여 클램핑 연산증폭기를 이용한 가산 회로로 구현하였다. 제작된 SDLVA의 측정 결과는 73 dB 이상의 소신호 이득과 10.1~12.2 dBm의 고주파 포화 출력 특성을 갖는다. 그리고 -70~0 dBm 입력 시 25 mV/ dB${\pm}$1.0 mV의 기울기를 갖고 ${\pm}$1.5 dB 이하의 선형 특성을 갖는 비디오 신호를 출력한다.