• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.949-952
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• 2005

We propose the hardwired distributed arithmetic which is applied to multiple constant multiplications and the fixed data path in the inner product of fixed coefficient as a result of variable radix-2 multi-bit coding. Variable radix-2 multi-bit coding is to reduce the partial product in constant multiplication and minimize the number of addition and shifts. At results, this procedure reduces the number of partial products that the required multiplication timing is shortened, whereas the area reduced relative to the DA architecture. Also, this architecture shows the best performance for DCT/IDCT and DWT architecture in the point of area reduction up to 20% from reducing the partial products up to 40% maximally.

• Korean Journal of Mathematics
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• v.14 no.1
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• pp.85-93
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• 2006

A good arithmetic random number generator should possess full period, uniformity and independence, etc. To obtain the excellent random number generator, many researchers have found good parameters. Also an initial seed is the important factor in random number generator. But, there is no theoretical guideline for using the initial seeds. Therefore, random number generator is usually used with the arbitrary initial seed. Through the empirical tests, we show that the choice of the initial values for the seed is important to generate good random numbers.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.464-467
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• 2001

A good arithmetic random number generator should possess full period, uniformity and independence, etc. To obtain the excellent random number generator, many researchers have found good parameters. Also an initial seed is the important factor in random number generator. But, there is no theoretical guideline for using the initial seeds. Therefore, random number generator is usually used with the arbitrary initial seed. Through the empirical tests, we show that the choice of the initial values for the seed is important to generate good random numbers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• Journal of Educational Research in Mathematics
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• v.26 no.3
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• pp.489-508
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• 2016

Number and operation is the most basic and crucial part in elementary mathematics but is also well known as a part that students have lots of difficulties. A lot of researches have been done in various ways to solve this problem but it can't be solved fundamentally by emphasizing calculation method and skill. So we need to go over it in terms of relevant arithmetical thinking. This study aims to diagnose the cause of an underachiever's difficulties about arithmetic and finds a prescription for her by analyzing her level of arithmetical thinking based on Guberman(2014) and understanding about arithmetic. To achieve this goal, we chose an 6th grader who's having a hard time particularly in number and operation among mathematics strands and conducted a case study carrying out arithmetical thinking level tests on two separate occasions and analyzing her responses. As a result of analyzing data, her arithmetical thinking corresponded to Guberman's first level and it is also turned out that student is suffering from some arithmetic concepts. We suggest several implications for teaching of arithmetic at elementary school in terms of the development of arithmetical thinking based on analysis result and discussion about it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.636-644
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• 2015

This research aims to suggest methods to improve object tracking performance by combining CAM shift algorithm with 8-way search window, and reduce arithmetic operation by reducing the number of frame used for tracking. CAM shift has its adverse effect in tracking methods using signature color or having difficulty in tracking rapidly moving object. To resolve this, moving search window of CAM shift makes it possible to more accurately track high-speed moving object after finding object by conducting 8-way search by using information at a final successful timing point from a timing point missing tracking object. Moreover, hardware development led to increased unnecessary arithmetic operation by increasing the number of frame produced per second, which indicates efficiency can be enhanced by reducing the number of frame used in tracking to reduce unnecessary arithmetic operation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.29-37
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• 1997

A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

• School Mathematics
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• v.12 no.3
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• pp.371-388
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• 2010

The goals of this study are to inquire middle school students' understanding about prime number and to propose pedagogical implications for school mathematics. Written questionnaire were given to 198 Korean seventh graders who had just finished learning about prime number and prime factorization and then 20 students participated in individual interviews for member checks. In defining prime and composite numbers, the students focused on distinguishing one from another by numbering of factors of agiven natural number. However, they hardly recognize the mathematical connection between prime and composite numbers related on the multiplicative structure of natural number. This study suggests that it is needed to emphasize the conceptual relationship between divisibility and prime decomposition and the prime numbers as the multiplicative building blocks of natural numbers based on the Fundamental Theorem of Arithmetic.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.1-5
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• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.