• 한국통신학회:학술대회논문집
• /
• 한국통신학회 1987년도 춘계학술발표회 논문집
• /
• pp.31-34
• /
• 1987

A new efficientcoding system which can transmit video conferenceof viedeophone signals at a 64kbps is proposed. In addition to the interframe and CRC (Conditional Repleni shment Coding) system, BTVQ (Binary Tree searched Vector Quantizer)and RLC (Run Length Coding) methods are incorporated. Couble buffer memory is used for simple comtrol of channel symbol transmission and memory underflow And also buffer memory onerfolw is easily controlled by the thresholds of a MAD (Moving Area Betector)

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.191-193
• /
• 2005

Flash memories are one of best media to support portable computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient data processing. F2PL improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process.

• 대한전자공학회논문지
• /
• 제25권8호
• /
• pp.927-936
• /
• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• 전기의세계
• /
• 제21권4호
• /
• pp.39-44
• /
• 1972

This paper describes a new approach for minimizing working memory spaces without loosing too much amount of computing time in the analysis of power system faults. This approach requires the decomposition of alrge power system into several small groups of subsystems, forms individual bus impedance matrics, store them in the auxiliary memory, later assembles them to the original total system by algorithms. And also the approach uses techniques for diagonalizing primitive impedances and expanding the system bus impedance matrices by adding a fault bus. These scheme ensures a remarkable savings of working storage and continous computations of fault currents and voltages with the voried fault locations.

• 한국해양공학회지
• /
• 제6권1호
• /
• pp.87-95
• /
• 1992

Recently, the robot actuator worked by the driving recovery-force of the thermo elastic martensitic transformation of shape memory alloys(SMA) has been studied. In general, such a SMA actuator necessitates a number of cyclic repeated motion, so that the investigation of gradual decrease of recovery force with repeated motion cycle as well as the prevention of such a degradation of shape memory effect(SME) are very important for the actual use of a robot actuator. However, such research and discussions about the degradation of SME are very few up to the present. Therefore, in this study, the characteristics of the cyclic deformation and degradation of SME of Ti-Ni alloy would be investigated and discussed in detail by current heat type fatigue tester, which is a newly designed fatigue tester by author. In addition, we will establish a new design concept for robot actuator from these result.

• 한국멀티미디어학회논문지
• /
• 제2권4호
• /
• pp.367-377
• /
• 1999

최근 들어 신속한 트랜잭션 처리를 요구하는 데이터베이스 응용이 확대되고 있다. 트랜잭션 처리 시스템에서 높은 성능을 달성하기 위한 한가지 방법으로 데이터베이스를 디스크가 아닌 주기억장치에 모두 상주시키는 것이다. 반도체 메모리의 집적도가 증가하고 가격이 하락함에 따라 모든 데이터베이스를 주기억장치에 상주시켜 트랜잭션 처리율을 높이기 위한 연구가 이루어지고 있다. 본 논문에서는 주기억장치 데이터베이스를 기반으로 한 고성능 트랜잭션 처리 시스템을 구현하기 위하여 새로운 병행수행 제어 기법과 회복 기법 그리고 저장 구조를 제안하며, 트랜잭션의 처리량과 응답속도로 평가되는 트랜잭션 처리 시스템 성능의 개선을 목적으로 한다.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
• /
• 제15권4호
• /
• pp.270-274
• /
• 2009

본 논문에서는 초소형 장치 상에서 적은 메모리만으로 효율적으로 연산 가능한 GF($2^m$) 상의 연산방법을 제안한다. 기존 구현들은 속도의 향상을 위한 곱셈연산 방법만을 제시하였으나, 본 논문에서는 곱셈 연산시 덧셈의 순서를 바꿈으로써 연산시 사용하는 메모리의 양을 줄이는 방법을 제시한다. 실험에 따르면, 본 논문에서 제안한 방법은 GF($2^{271}$)의 곱셈연산에서 이전에 제안된 방법들과 비교해 비슷한 수행 시간을 사용하면서 약 20% 적은 메모리 사용량을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권1호
• /
• pp.15-22
• /
• 2017

Although there are many efficient techniques to minimize the speed gap between processor and the memory, it remains a bottleneck for various commercial implementations. Since secondary memory technologies are much slower than main memory, it is challenging to match memory speed to the processor. Usually, hard disk drives include semiconductor caches to improve their performance. A hit in the disk cache eliminates the mechanical seek time and rotational latency. To further improve performance a divided disk cache, subdivided between metadata and data, has been proposed previously. We propose a new algorithm to apply the SSD that is flash memory-based solid state drive by applying FTL. First, this paper evaluates the performance of such a disk cache via simulations using DiskSim. Then, we perform an experiment to evaluate the performance of the proposed algorithm.

• International journal of advanced smart convergence
• /
• 제6권1호
• /
• pp.39-43
• /
• 2017

As the industry grows, the amount of data grows exponentially, and data analysis using these serves as a predictable solution. As data size increases and processing speed increases, it has begun to be applied to new fields by combining artificial intelligence technology as well as simple big data analysis. In this paper, we propose a method to quickly apply a machine learning based algorithm through efficient resource allocation. The proposed algorithm allocates memory for each attribute. Learning Distinct of Attribute and allocating the right memory. In order to compare the performance of the proposed algorithm, we compared it with the existing K-means algorithm. As a result of measuring the execution time, the speed was improved.

• 한국컴퓨터정보학회논문지
• /
• 제22권3호
• /
• pp.1-8
• /
• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.