• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Applied Chemistry for Engineering
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• v.23 no.6
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• pp.515-520
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• 2012

In this review, the fabrication of silicon based memory capacitor and organic memory thin film transistors (TFTs) was discussed for their potential identification tag applications and biosensor applications. Metal or non-metal nanoparticles (NPs) could be capped with chemicals or biomolecules such as protein and oligo-DNA, and also be self-assembly monolayered on corresponding target biomolecules conjugated dielectric layers. The monolayered NPs were formed to be charging elements of a nano floating gate layer as forming organic memody deivces. In particular, the strong and selective binding events of the NPs through biomolecular interactions exhibited effective electrostatic phenomena in memory capacitors and TFTs formats. In addition, memory devices fabricated as organic thin film transistors (OTFTs) have been intensively introduced to facilitate organic electronics era on flexible substrates. The memory OTFTs could be applicable eventually to the development of new conceptual devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.219-219
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• 2010

기존의 플로팅 타입의 메모리는 소자의 소형화에 따른 인접 셀 간의 커플링 현상과 전계에 따른 누설전류의 증가 등과 같은 문제가 발생한다. 이에 대한 해결책으로서 전하 저장 층을 폴리실리콘에서 유전체를 사용하는 SONOS 형태의 메모리와 NFGM (Nano-Floating Gate Memory)연구가 되고 있다. 그러나 높은 구동 전압, 느린 쓰기/지우기 속도 그리고 10년의 전하보존에 대한 리텐션 특성을 만족을 시키지 못하는 문제가 있다. 이러한 문제를 해결 하고자 터널베리어를 엔지니어링 하는 TBM (Tunnel Barrier Engineering Memory) 기술에 대한 연구가 활발히 진행 중이다. TBM 기술은 터널 층을 매우 얇은 다층의 유전체를 사용하여 전계에 따른 터널베리어의 민감도를 증가시킴으로써 빠른 쓰기/지우기 동작이 가능하며, 10년의 전하 보존 특성을 만족 시킬 수 있는 차세대 비휘발성 메모리 기술이다. 또한 고유전율 물질을 터널층으로 이용하면 메모리 특성을 향상 시킬 수가 있다. 일반적으로 TBM 기술에는 VARIOT 구조와 CRESTED 구조로 나눠지는데 본 연구에서는 두 구조의 장점을 가지는 Staggered tunnel barrier 구조를 $Si_3N_4$와 HfAlO을 이용하여 디자인 하였다. 이때 HfO2와 Al2O3의 조성비는 3:1의 조성을 갖는다. $Si_3N_4$와 HfAlO을 각각 3 nm로 적층하여 리세스(Recess) 구조의 트랜지스터를 제작하여 차세대 비휘발성 메모리로써의 가능성을 알아보았다.