• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.335.2-335.2
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• 2016

The fixed negative charge of the Al2O3 passivation layer gives excellent passivation performance for both n-type and p-type silicon wafers. For the best passivation quality, annealing is known to be a prerequisite step and a lot of studies concerning annealing effect on the passivation characteristics have been performed. Meanwhile, for manufacturing a crystalline silicon solar cell, firing process is applied to the Al2O3 passivation layer. Therefore, study on not only annealing effect but also on firing effect is necessary. In this work, Al2O3 passivation performance (minority carrier lifetime) for p-type silicon wafer was evaluated with Quasi-Steady-State Photoconductance(QSSPC) measurement after annealing at different temperatures. For the samples which showed different aspects, C-V measurement was performed for the cause - whether it is due to the chemical effect or field-effect. The change in Al2O3 passivation property after firing processes was investigated and the mechanism for the change could be estimated.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.429-429
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• 2012

To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.126.1-126.1
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• 2011

박막형 태양전지의 효율 향상을 위하여 광확산 패턴이 형성된 기판을 제작하고 이를 이용하여 비정질 실리콘 박막 태양전지를 제작하였다. 나노 임프린트 방법을 사용하여 제작된 광확산 패턴은 불규칙한 마이크로-나노 크기의 미세구조를 가지고 있어 빛의 확산투과 비율을 향상시켜주는 역할을 하였다. 제작된 광확산 기판위에 TCO물질을 증착하고, PECVD법을 사용하여 비정질 실리콘 p-i-n 접합 구조를 형성하였다. 제작된 태양전지 소자를 1.5 AM의 조건에서 I-V 특성을 분석하였으며, 비교군으로 사용된 일본 Asahi 사의 U-type glass에 비해 높은 Jsc 값을 나타내었다. 또한 외부양자효율을 측정함으로써 광확산 패턴에 의한 양자효율 변화를 확인 할 수 있었다.

• Current Applied Physics
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• v.18 no.11
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• pp.1268-1274
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• 2018

We have investigated the effects of chemical rounding (CR) on the surface passivation and/or antireflection performance of $AlO_{x^-}$ and $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters with two different boron doping concentrations, and on the performance of bifacial n-PERT Si solar cells with a front pyramid textured $p^+$-emitter. From experimental results, we found that chemical rounding markedly enhances the passivation performance of $AlO_x$ layers on pyramid textured $p^+$-emitters, and the level of performance enhancement strongly depends on boron doping concentration. Meanwhile, chemical rounding increases solar-weighted reflectance ($R_{SW}$) from ~2.5 to ~3.7% for the $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters after 200-sec chemical rounding. Consequently, compared to non-rounded bifacial n-PERT Si cells, the short circuit current density Jsc of 200-sec-rounded bifacial n-PERT Si cells with ~60 and ${\sim}100{\Omega}/sq$ $p^+$-emitters is reduced by 0.8 and $0.6mA/cm^2$, respectively under front $p^+$-emitter side illumination. However, the loss in the short circuit current density Jsc is fully offset by the increased fill factor FF by 0.8 and 1.5% for the 200-sec-rounded cells with ~60 and ${\im}100{\Omega}/sq$ $p^+$-emitters, respectively. In particular, the cell efficiency of the 200-sec-rounded cells with a ${\sim}100{\Omega}/sq$ $p^+$-emitter is enhanced as a result, compared to that of the non-rounded cells. Based on our results, it could be expected that the cell efficiency of bifacial n-PERT Si cells would be improved without additional complicated and costly processes if chemical rounding and boron doping processes can be properly optimized.

• Current Photovoltaic Research
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• v.6 no.2
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• pp.62-67
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• 2018

Multi-wire busbar-type bifacial n-type Si solar cells have been used for the fabrication of monofacial and bifacial photovoltaic (PV) module, where bifacial module was equipped with transparent backsheet while monofacial module was prepared using white backsheet. The comparison of six-day accumulated power production obtained from outdoor test under gray cement ground conditions using 60cell monofacial and bifacial PV modules suggested the bifacial gain of over 20% could be achieved. Furthermore, the outdoor evaluation tests of bifacial modules with different ground conditions such as cement (reference), green paint, white paint and green artificial grass, were performed. It turned out white paint showed the best albedo and thus the highest power production, while green paint and artificial grass showed less power generation than cement ground.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.5
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• pp.195-199
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• 2008

Production of the silicon feedstock for the semiconductor industry cannot meet the requirement for the solar cell industry because the production volume is too small and production cost is too high. This situation stimulates the solar cell industry to try the lower grade silicon feedstock like UMG (Upgraded Metallurgical Grade) silicon of 5$\sim$6 N in purity. However, this material contains around 1 ppma of dopant atoms like boron or phosphorous. Calculation of the composition profile of these impurities using segregation coefficient during crystal growth makes us expect the change of the type from p to n : boron rich area in the early solidified part and phosphorous rich area in the later solidified part of the silicon ingot. It was expected that the change of the growth speed during the silicon crystal growth is effective in controlling the amount of the metal impurities but not effective in reducing the amount of dopants.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.278-278
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• 2009

A photovoltaic device consisting of arrays of radial p-n junction wires enables a decoupling of the requirements for light absorption and carrier extraction into orthogonal spatial directions. Each individual p-n junction wire in the cell is long in the direction of incident light, allowing for effective light absorption, but thin in orthogonal direction, allowing for effective carrier collection. To fabricate radial p-n junction solar cells, p or n-type vertical Si wire cores need to be produced. The majority of Si wires are produced by the vapor-liquid-solid (VLS) method. But contamination of the Si wires by metallic impurities such as Au, which is used for metal catalyst in the VLS technique, results in reduction of conversion efficiency of solar cells. To overcome impurity issue, top-down methods like noble metal catalytic etching is an excellent candidate. We used noble metal catalytic etching methods to make Si wire arrays. The used noble metal is two; Au and Pt. The method is noble metal deposition on photolithographycally defined Si surface by sputtering and then etching in various BOE and $H_2O_2$ solutions. The Si substrates were p-type ($10{\sim}20ohm{\cdot}cm$). The areas that noble metal was not deposited due to photo resist covering were not etched in noble metal catalytic etching. The Si wires of several tens of ${\mu}m$ in height were formed in uncovered areas by photo resist. The side surface of Si wires was very rough. When the distance of Si wires is longer than diameter of that Si nanowires are formed between Si wires. Theses Si nanowires can be removed by immersing the specimen in KOH solution. The optimum noble metal thickness exists for Si wires fabrication. The thicker or the thinner noble metal than the optimum thickness could not show well defined Si wire arrays. The solution composition observed in the highest etching rate was BOE(16.3ml)/$H_2O_2$(0.44M) in Au assisted chemical etching method. The morphology difference was compared between Au and Pt metal assisted chemical etching. The efficiencies of radial p-n junction solar Cells made of the Si wire arrays were also measured.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.322-322
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• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.366-366
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• 2010

Simulation Program (AFORS-HET 2.4.1) was used, include the basic structure of crystalline silicon thin film as above, below Intrinsic a-Si:H films bonded symmetrical structure (Symmetrical structure) were used. Efficiency with variation of the concentration was grown by the a-Si p-type with increasing concentrations of Na, efficiency with increasing a-Si n-type of Nd Concentrations was not changed, was decreased rapidly when concentrations were decreased. Efficiency was increased when c-Si n-type of Nd concentration was increased, otherwise efficiency was decreased when concentration was decreased.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.166-169
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• 2006

We fabricated hexagonal copper sulfide $Cu_2S$ nanowires to obtain a larger contact area of $Cu_2S/CdS$ solar cell. Copper sulfide nanowires were grown on Cu foil at room temperature by gas-sol id reaction. The size, density and shape of nanowires seemed to be affected by the change or reaction time temperature, crystallographic orientation of Cu foil, and molar ratio of the mixed gas. We controled the length and the diameter of the nanowires and we obtained suitable nanowire arrays which has fitting size for uniform deposition with n-type CdS. CdS layer was deposited on the nanowire array by electrodeposition and it seemed to be uniform. The $Cu_2S/CdS$ nanowires/CdS junction showed diode characteristics, A large contact area is expected with the $Cu_2S/CdS$ nanowire structure as compared with the $Cu_2S/CdS$ thin film.