• Journal of KIISE
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• v.42 no.2
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• pp.155-161
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• 2015

It is difficult and cumbersome to figure out whether a multithread program runs with concurrency bugs, such as data races and atomicity violations, because there are many possible executions of the program and a lot of the defects are hard to reproduce. Hence, monitoring techniques for collecting and analyzing the information from program execution, such as thread executions, memory accesses, and synchronization information, are important to locate data races for debugging multithread programs. This paper presents an efficient and practical monitoring tool, called VcTrace, that analyzes the partial ordering of concurrent threads and events during an execution of the program based on the vector clock system. Empirical results on C/C++ benchmarks using Pthreads show that VcTrace is a sound and practical tool for on-the-fly data race detection as well as for analyzing multithread programs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Journal of Information Management
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• v.29 no.3
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• pp.1-26
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• 1998

The loop is a fundamental for the parallelism exploiting as it has a large portion of execution time for sequential Java program on the parallel machine. This paper proposes the method of exploiting the implicit parallelism through the analysis of data dependence in the existing Java programming language having a single loop structure. The parallel code generation method through the restructuring compiler and the translation method of Java source program into multithread statement, which is supported in the level of the Java programming language, are also proposed here. The performance test of the program translated into the thread statement is conducted using the trip count of loop and the thread count as parameters. The restructuring compiler makes it possible for users to reduce overhead and exploit parallelism efficiently in the Java programming.

• Journal of Korea Game Society
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• v.14 no.5
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• pp.25-34
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• 2014

In this paper, the weak point of AOS jenre online game which occupies the majority of Korea game market of 2014 year is analyzed and to solve the problem, the enhanced design and implementation content is introduced. The proposed game is based on the custom AOS jenre format but has the TPS view and nontargeting format to enhance the action feel. To enhance the game quality, graphics, animation, effect and sound resources are organized. Game server is implemented by multithread of IOCP model to support many clients. The technical issue and design method of client and server are described.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.526-528
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• 2001

EJB는 Sun사에서 발표한 분산 객체 구조에 맞는 서버쪽 컴포넌트 아키텍쳐이다. EJB를 사용하면 다중 네트워크 환경에서 애플리케이tus의 디자인과 개발, 배포가 쉬워진다. 개발자는 하부 사항에 대해 신경쓰지 않고 상위 레벨에서 애플리케이션을 설계할 수 있다. EJB 1.1 명세서는 그러한 내용을 나타내고 있는 명세서이다. 하지만 이 명세에서는 멀티 스레드를 허용하지 않는다. 멀티 스레드는 프로그래밍에서 상당히 유용한 것으로 멀티 스레드를 사용하면 다른 오브젝트에 영향을 주지 않으면서 작업을 수행할 수 있는 등 여러 가지 이점이 많다. 본 논문에서는 이러한 이점을 살려서 명세서에 따르면서 멀티 스레드를 생성하는 방법에 대해 알아보고자 한다. 본 논문에서 제시하는 방법은 3가지이고 각각 장단점이 따른다 .

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.5
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• pp.361-367
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• 2014

In this paper, task scheduling and load balancing methods of multifrontal solution methods of finite element structural analysis in a modern multicore machine are introduced. Many structural analysis problems have generally irregular grid and many kinds of properties and materials. These irregularities and heterogeneities lead to bottleneck of parallelization and cause idle time to analysis. Therefore, task scheduling and load balancing are desired to reduce inefficiency. Several kinds of multithreaded parallelization methods are presented and comparison between static and dynamic task scheduling are shown. To reduce the idle time caused by irregular partitioned subdomains, computational load balancing methods, Balancing all tasks and minmax task pairing balancing, are invented. Theoretical and actual elapsed time are shown and the reason of their performance gap are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1144-1152
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• 2000

In order to guarantee the user-requested quality-of-service(QoS) and keep the network utilization at maximum it is required to manage the network performance continuously after the network installation. The performance management function should provide the useful information for the network expansion and the capacity reallocation in the future. Currently the TINA provides the specification of the management function of configuration management connection management and fault management ; but the management function of performance management and security management are not well-defined yet. In this paper we propose a TINA-based performance management architecture for the efficient performance management of the heterogeneous networks or NEs with TMN and SNMP management functions. And we examine the proposed architecture into the ATM network (with SNMP and TMN) monitoring. The proposed architecture is based on the distributed processing architecture and the concept the TMN perfo mance management. The proposed architecture have been designed and implemented in multiprocess and multithread structure.

• Proceedings of the Korean Society of Computer Information Conference
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• 2016.07a
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• pp.3-4
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• 2016

멀티스레드 프로그램의 수행 중에 발생할 수 있는 자료경합은 프로그래머가 의도하지 않은 비결정적 수행으로 인해 신뢰할 수 없는 프로그램의 결과를 발생시킨다. 이러한 자료경합의 디버깅을 위해서 시간 및 자원적 비용이 과도하게 발생하기 때문에 프로그램의 수행 중에 이를 용인하고 치유하는 것이 중요하다. 본 논문은 멀티스레드 프로그램을 대상으로 소프트웨어 트랜잭셔널 메모리(STM)를 사용하여 공유변수에 대한 트랜잭션 영역을 설정하고 공유변수에 대한 이벤트 충돌 유형에 따른 자료경합 치유기법을 설계한다. 최종적으로는 프로그램 수행 중에 자료경합을 치유하는 기법의 실현가능성을 확인한다.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.336-337
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• 2011

The popularity of general purpose GPU（GPGPU）makes the CPU-GPGPU heterogeneous architecture normal. Therefore, tradeoff the usage of CPU and GPGPU becomes a way to improve performance of programs. In this work, we exploit the properties of the CPU-GPGPU heterogeneous architecture and use them to accelerate the content based chunking operation of deduplication. We built a prototype system which is able to coordinate CPU and GPGPU to chunk file and has been proven to have a better performance compared to using either CPU or GPGPU alone.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1518-1523
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• 2012

In this study, the novel digital filtering algorithms are implemented to suppress the noisy characteristics embedded in ambulatory electrocardiogram signals by an android smartphone platform. With this aim, Graphical User Interface (GUI) is designed and implemented by utilizing multithread-Java programming to realize Finite Impulse Response and Infinite Impulse Response filter. With simulating our implemented digital filters built in an android smartphone, we can find the fact that we can efficiently suppresses the noisy characteristics due to baseline wandering and 60 Hz powerline source fluctuations especially in electrocardiograms.