• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.30-43
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• 2013

Multicore and multiprocessor systems with dynamic voltage scaling architectures are being used as one of the solutions to satisfy the growing needs of high performance applications with low power constraints. An important aspect that has propelled this solution is effective task/application scheduling and mapping algorithms for multiprocessor systems. This work proposes an energy aware, offline, probability-based unified scheduling and mapping algorithm for multiprocessor systems, to minimize the number of processors used, maximize the utilization of the processors, and optimize the energy consumption of the multiprocessor system. The proposed algorithm is implemented, simulated and evaluated with synthetic task graphs, and compared with classical scheduling algorithms for the number of processors required, utilization of processors, and energy consumed by the processors for execution of the application task graphs.

• Journal of the Korea Society for Simulation
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• v.8 no.1
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• pp.35-49
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• 1999

The CC-NUMA based, distributed shared memory is an emerging architecture for multiprocessor computer systems because of its scalability and easy of programming. In this paper, we analyzed performance of a ring-based, CC-NUMA multiprocessor computer system using a commercial workload targeted for popular OLTP applications. Based on the traces collected from real machines, the characteristics of the commercial workload could be obtained. The simulation results showed that the bottleneck on the ring could be effectively removed by using a dual ring structure. We believe our simulation methodology and results will help us to design better multiprocessor computer systems for commercial application domains.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.421-428
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• 2008

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.140.3-140
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• 2001

This paper analyzes a blocking that is due to shared resource in multiprocessor system. A proposed analysis for shared resource suggests a scalable and amendable scheduling method about task allocation. An equation of shared resource blocking is proposed by a throughput at common bus and a ratio of throughput during time period, it is included a parameter of tasks scheduling. Using this equation, a new guideline for task allocation of multiprocessor is presented. Finally, in proposed system a model simulations for the proposed blocking model is given by a deterministic ratio of shared resource.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.4
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• pp.145-157
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• 2007

OpenMP is an attractive parallel programming model for a chip multiprocessor because there is no standard parallel programming method for a chip multiprocessor and it is easy to write a parallel program in OpenMP. Then, chip multiprocessor systems can have various architectures according to target application programs. So, we need to implement OpenMP in different way for each system. In this paper, we propose the implementation and the effective translation of major OpenMP directives for a chip multiprocessor without using OS to improve the performance without using special hardware and without extending the OpenMP directives. We present the experimental results on our target platform CT3400.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.890-900
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• 1999

In homogeneous multiprocessor systems, the task allocation algorithm which equally assigns tasks to processors if possible is generally used. But this algorithm is not suitable to accomplish to accomplish effective task allocation in heterogeneous multiprocessor systems. JSQ (Join the Shortest Queue) algorithm is often used in heterogeneous multiprocessor systems. Unfortunately, JSQ algorithm is not efficient when the differences of capabilities of processors are far large. To solve this problem, we suggest a heuristic task allocation algorithm that makes use of dynamic information such as task arrival time, task service time, and number of finished tasks. The results of simulation show that the proposed heuristic allocation algorithm improves the system performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.733-735
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• 2012

Real-Time Aperiodic Tasks Scheduling Using Synthetic Utilization on Multiprocessor Systems has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.

• ETRI Journal
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• v.30 no.1
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.619-622
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• 1986

컴퓨터 기술의 발달에 따라 디지탈 전산기는 연산처리 능력이 더욱 빨라지고, 더욱 큰 기억용량을 갖게 되었다. 따라서 산업공정, 화학프랜트, 원자력발전 및 항공분야 등의 복잡한 연속 동특성계에 대한 실시간 시뮬레이션이 가능하게 되었다. 특히 복잡한 연속 동특성계의 시뮬레이션 목적으로 Multiprocessor 형태의 전산기가 개발되었다. 이 Multiprocessor형태의 전산기는 D/A 변환기와 A/D 변환기를 갖추므로써 실시간 실물 모의시험(A real time hardware-in-the-loop simulation) 시의 컴퓨터와 외부장비와의 데이타 전달이 용이하여 졌다. 본 연구에서는 비행체의 비행자세를 제어하기 위한 조종장치의 설계해석 및 성능시험을 위하여 Multiprocessor를 이용하여 실시간 실물 모의실험이 가능함을 보였다. 본 시뮬레이션에 사용된 전산기는 AD10 전산기이다.