• Journal of Navigation and Port Research
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• v.35 no.5
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• pp.415-421
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• 2011

The purposes of this study were to identify the economic impacts of hosting a marine leisure event and thus provide fundamental information that helps maximize the economic value of the event. In order to accomplish such purposes, this study employed both an economic impact analysis(EIA) using regional input output model and a benefit and cost ratio analysis(BCR). In specific, this study utilized a survey method with a total of 300 event visitors and 70 foreign players and thus collected expenditure data from 110 valid out of town visitors and 58 foreign players. In addition, investment expenditure data were collected from the host city official. Accordingly, EIA and BCR indicated following findings. First, the total direct impact from both visitors and players was 387 million Won and this direct impact resulted in output multiplier effect(OME) of 591 million Won, value added multiplier effect(VAME) of 306 million Won and income multiplier effect(IME) of 252 million Won. Second, the host city's investment expenditure created OME, VAME and IME of 825, 432 and 366 million Won, respectively. In conclusion, these findings suggest that in order to effectively boost potential economic benefits, more marketing efforts development policies should be implemented for increasing the number of out of town visitors and the amount of spendings from them.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.39-44
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• 2011

This paper proposes the new high-performance circuit architecture of the transform and quantization for unified video CODEC. The proposed architecture can be applied to all kinds of transforms and quantizations for the video compression standards such as JPEG, MPEG-1/2/4, H.264 and VC-1. We defined the permutation matrices to reorder the transform matrix of the $8{\times}8$ DCT and partitioned the reordered $8{\times}8$ transform matrix into four $4{\times}4$ sub-matrices. The $8{\times}8$ DCT is performed by repeating the $4{\times}4$ DCT's based on the reordered and partitioned transform matrices. Since our circuit accepts the transform coefficients from the users, it can be extended very easily to cover any kind of DCT-based transforms for future standards. The multipliers in the DCT circuit are shared by the quantization circuit in order to minimize the circuit size. The quantization circuit is merged into the DCT circuit without any significant increase of circuit resources and processing time. We described the proposed DCT and quantization circuit at RTL, and verified its operation on FPGA board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1621-1627
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• 2011

This study investigates both backward and forward multipliers of human capital in the field of information technology in order to evaluate human resources programs which were executed in the public sectors. Dynamic interindustry linkages analysis was employed as a methodology after classifying human capitals related to information technology into 9 industries. First, empirical findings showed that there are economic externalities in the IT HRD programs when the formation of human capital increases with more investment in them. Second, another finding was that the effect of HRD programs could be powerful when HRD programs were closely connected with R&D programs, showing that R&D programs among IT HRD programs have huge backward linkage effect. In addition, IT service sector has its own spill-over effect to other industries. Third, however, small budget and one off HRD programs should be considered as a negative price synergy effect. Finally, overall economic feasibility of IT HRD programs turned out to be excellent with consideration of their own economic direct and indirect effect.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.4
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• pp.249-256
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• 2019

This paper presents an optimization framework of electrical impedance tomography for characterizing electrical conductivity profiles of concrete structures in two dimensions. The framework utilizes a partial-differential-equation(PDE)-constrained optimization approach that can obtain the spatial distribution of electrical conductivity using measured electrical potentials from several electrodes located on the boundary of the concrete domain. The forward problem is formulated based on a complete electrode model(CEM) for the electrical potential of a medium due to current input. The CEM consists of a Laplace equation for electrical potential and boundary conditions to represent the current inputs to the electrodes on the surface. To validate the forward solution, electrical potential calculated by the finite element method is compared with that obtained using TCAD software. The PDE-constrained optimization approach seeks the optimal values of electrical conductivity on the domain of investigation while minimizing the Lagrangian function. The Lagrangian consists of least-squares objective functional and regularization terms augmented by the weak imposition of the governing equation and boundary conditions via Lagrange multipliers. Enforcing the stationarity of the Lagrangian leads to the Karush-Kuhn-Tucker condition to obtain an optimal solution for electrical conductivity within the target medium. Numerical inversion results are reported showing the reconstruction of the electrical conductivity profile of a concrete specimen in two dimensions.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.105-111
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• 2006

Cryptographic application and coding theory require operations in finite field $GF(2^m)$. In such a field, the area and time complexity of implementation estimate by memory and time delay. Therefore, the effort for constructing an efficient multiplier in finite field have been proceeded. Massey-Omura proposed a multiplier that uses normal bases to represent elements $CH(2^m)$ [11] and Agnew at al. suggested a sequential multiplier that is a modification of Massey-Omura's structure for reducing the path delay. Recently, Rayhani-Masoleh and Hasan and S.Kwon at al. suggested a area efficient multipliers for modifying Agnew's structure respectively[2,3]. In [2] Rayhani-Masoleh and Hasan proposed a modified multiplier that has slightly increased a critical path delay from Agnew at al's structure. But, In [3] S.Kwon at al. proposed a modified multiplier that has no loss of a time efficiency from Agnew's structure. In this paper we will propose a multiplier by modifying Rayhani-Masoleh and Hassan's structure and the area-time complexity of the proposed multiplier is exactly same as that of S.Kwon at al's structure for type-II optimal normal basis.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.35 no.5
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• pp.249-257
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• 2022

This paper presents an improved computational framework for the direct-solution-based finite element tearing and interconnecting (FETI) algorithm. The FETI-local algorithm is further improved herein, and localized Lagrange multipliers are used to define the interface among its subdomains. Selective inverse entry computation, using a property of the Boolean matrix, is employed for the computation of the subdomain interface stiffness and load, in which the original FETI-local algorithm requires a full matrix inverse computation of a high computational cost. In the global interface computation step, the original serial computation is replaced by a parallel multi-frontal method. The performance of the improved FETI-local algorithm was evaluated using a numerical example with 64 million degrees of freedom (DOFs). The computational time was reduced by up to 97.8% compared to that of the original algorithm. In addition, further stable and improved scalability was obtained in terms of a speed-up indicator. Furthermore, a performance comparison was conducted to evaluate the differences between the proposed algorithm and commercial software ANSYS using a large-scale computation with 432 million DOFs. Although ANSYS is superior in terms of computational time, the proposed algorithm has an advantage in terms of the speed-up increase per processor increase.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.285-290
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• 2023

Compressors are widely used in high-speed electronic systems and are used to reduce the number of operands in multiplier. The proposed compressor is constructed based on the m-GDI(: modified gate diffusion input) to reduce the propagation delay time. This paper is compared the performance of compressors by applying 4-2, 5-2 and 6-2 m-GDI compressors to the multiplier, respectively. As a simulation results, compared to the 8-bit Dadda multiplier using the 4-2 and 6-2 compressor, the multiplier using the 5-2 compressor is reduced propagation delay time 13.99% and 16.26%, respectively. Also, the multiplier using the 5-2 compressor is reduced PDP(: Power Delay Product) 4.99%, 28.95% compared to 4-2 and 6-2 compressor, respectively. However, the multiplier using the 5-2 compression circuit is increased power consumption by 10.46% compared to the multiplier using the 4-2 compression circuit. In conclusion, the 8-bit Dadda multiplier using the 5-2 compressor is superior to the multipliers using the 4-2 and 6-2 compressors. The proposed circuit is implemented using TSMC 65nm CMOS process and its feasibility is verified through SPECTRE simulation.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.6D
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• pp.577-585
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• 2010

Traffic accidents are caused by several factors such as drivers, vehicles, and road environment. It is necessary to investigate and analyze them in advance to prevent similar and repetitive traffic accidents. Especially, the human factor is most significant element and traffic accidents by drinking-driving caused from human factor have become social problem to be paid attention to. The study analyzes traffic accidents resulting from drinking-driving and the effects of driver's attributes and environmental factors on them. The study is composed as two parts. First, the log-linear model is applied to analyze that accidents by drinking or non-drinking driving associate with road geometry, weather condition and personal characteristics. Probability is tested for drinking-driving accidents relative to non-drinking drive accidents. The study analyzes probability differences between genders, between ages, and between kinds of vehicles through odds multipliers. Second, traffic accidents related to drinking are classified into property damage, minor injury, heavy injury, and death according to their severity. Heavy injury is more serious than minor one and death is more serious than heavy injury. The ordinal regression models are established to find effecting factors on traffic accident severity.